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1Introduction............................................................................................................................3
2 The Design Case and Requirements ....................................................................................... 3
3Background............................................................................................................................5
3.1 The AHB Protocol................................................................................................................5
3.2 The SystemVerilog interface Construct................................................................................ 7
3.3 SystemVerilogAssertions.....................................................................................................9
4 Implementation Architecture................................................................................................12
5 The RTL Code......................................................................................................................15
5.1Interfaces............................................................................................................................15
5.2 BusCore.............................................................................................................................19
5.3 BusHubs............................................................................................................................22
5.4 MasterProxy.......................................................................................................................22
5.5 Bus Top-Level and Example Subsystem............................................................................ 24
5.6Assertions...........................................................................................................................27
6 Synthesis...............................................................................................................................30
7Conclusions..........................................................................................................................33 |
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