一篇很好的国外DLL博士学位论文！

stoneduan

太一般

ysg9999

赞a!

xcoder

下下来看看

cuckoohui

看看先

smartboy918

thanks

superrabbit

留学生写的~~

layes

本是不想下的，还是想看看外国博士论文什么样子

cherryknight

:victory: eetop

meeda

Thanks !

yuqiumax

A DELAY-LOCKED LOOP FOR MULTIPLE CLOCK
PHASES/DELAYS GENERATION
是这篇论文

A Dissertation Presented to The Academic Faculty by
Cheng Jia
In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in the School of Electrical and Computer Engineering
Georgia Institute of Technology
December, 2005


SUMMARY
This thesis presents our work in the design of a Delay-Locked Loop (DLL) for the
generation of multiple clock phases/delays. A novel DLL design is proposed with several
new techniques to help achieve wide lock range, short locking time, and reduced jitter.
The DLL can be used for a variety of applications which require precise time intervals or
phase shifts.

TABLE OF CONTENTS
Page
ACKNOWLEDGEMENTS iii
LIST OF TABLES vi
LIST OF FIGURES vii
SUMMARY x
CHAPTER
1 Introduction 1
1.1 Motivation 1
1.2 Problem statement 4
1.3 Thesis contributions 5
1.4 Thesis organization 6
2 Previous work 7
2.1 DLL overview 7
2.2 DLL design 16
3 Overall approach 33
3.1 DLL for BIST application 33
3.2 DLL for other clock management applications 36
4 Design of the DLL 37
4.1 DLL architecture design 37
4.2 DLL component design 37
4.3 S-domain analysis of the DLL 50
5 Layout of the DLL 52
5.1 Improving matching 52
5.2 Reducing substrate and power noise 55
5.3 Minimizing crosstalk 56
6 Performance evaluation 58
6.1 Performance summary 58
6.2 Process variation 58
6.3 Temperature variation 61
6.4 Power grid glitch 63
6.5 Mismatch 64
6.6 Jitter 66
6.7 Static phase error 69
6.8 Lock range 69
6.9 Lock time 70
7 DLL BIST 71
8 Conclusion 78
REFERENCES 80
VITA 84