Agilent公司射频设计教程

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A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

Abstract—This paper describes a 10-bit 30-MS/s subsampling
pipelined analog-to-digital converter (ADC) that is implemented
in a 0.18 m CMOS process. The ADC adopts a power efficient
amplifier sharing architecture in which additional switches are introduced
to reduce the crosstalk between the two opamp-sharing
successive stages. A new configuration is used in the first stage
of the ADC to avoid using a dedicated sample-and-hold amplifier
(SHA) circuit at the input and to avoid the matching requirement
between the first multiplying digital-to-analog converter (MDAC)
and flash input signal paths. A symmetrical gate-bootstrapping
switch is used as the bottom-sampling switch in the first stage to
enhance the sampling linearity. The measured differential and integral
nonlinearities of the prototype are less than 0.57 least significant
bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The
ADC exhibits higher than 9.1 effective number of bits (ENOB) for
input frequencies up to 30 MHz, which is the twofold Nyquist rate
(fs/2), at 30 MS/s. The ADC consumes 21.6mWfrom a 1.8-V power
supply and occupies 0.7 mm2, which also includes the bandgap
and buffer amplifiers. The figure-of-merit (FOM) of this ADC is
0.26 pJ/step.
Index Terms—Analog-to-digital converter, opamp sharing,
sample-and-hold, SHA-less, subsampling.

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