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EETOP 创芯网论坛 (原名：电子顶级开发网)»论坛 › IC 设计及制造（半导体、微电子） › 数字IC设计【ASIC|IC前端|FPGA】 › 数字IC设计资料(IC前端|FPGA|ASIC) › One concern about: "Verilog: Frequently Asked Questi ...

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One concern about: "Verilog: Frequently Asked Questions"

发表于 2008-6-17 23:56:29 | 显示全部楼层 |阅读模式

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There are several posts about the book "Verilog: Frequently Asked Questions". I didn't check all of them, but looks they are all missing the chapter 3, which is about verification.

This book is very well. I am wondering if someone could help to make up this defects.

Thanks
Tedious

about, check, several, someone

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发表于 2008-6-18 09:46:35 | 显示全部楼层

yes, you are right.
all of the versions available from Internet are the same... with loss of chapter 3.

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发表于 2008-6-18 11:50:07 | 显示全部楼层

I have the complete version. If you like, I would upload that.

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发表于 2008-6-18 21:42:24 | 显示全部楼层

原帖由 vertyang 于 2008-6-18 11:50 发表

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I have the complete version. If you like, I would upload that.

Yes, could you please upload the missing chapter?

Thank you in advance!!

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发表于 2008-6-19 07:21:00 | 显示全部楼层

对，关键的一章缺失了

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发表于 2008-9-16 14:51:33 | 显示全部楼层

需要这本书！

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