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Verilog HDL Quick Reference Guide,IEEE 1364-2001的精华
不用再看几百页的IEEE 1364-2001了。
Table of Contents
1.0 New Features In Verilog-2001 ..................................................... 1
2.0 Reserved Keywords ...................................................................... 2
3.0 Concurrency ................................................................................. 3
4.0 Lexical Conventions ..................................................................... 3
4.1 Case Sensitivity ................................................................... 3
4.2 White Space Characters ....................................................... 3
4.3 Comments ............................................................................ 3
4.4 Attributes ............................................................................. 3
4.5 Identifiers (names) ............................................................... 4
4.6 Hierarchical Path Names ..................................................... 4
4.7 Hierarchy Scopes and Name Spaces ................................... 4
4.8 Logic Values ........................................................................ 5
4.9 Logic Strengths .................................................................... 5
4.10 Literal Real Numbers .......................................................... 5
4.11 Literal Integer Numbers ...................................................... 6
5.0 Module Definitions ....................................................................... 7
5.1 Module Items ....................................................................... 7
5.2 Port Declarations ................................................................. 8
6.0 Data Type Declarations .............................................................. 10
6.1 Net Data Types .................................................................. 10
6.2 Variable Data Types .......................................................... 12
6.3 Other Data Types ............................................................... 14
6.4 Vector Bit Selects and Part Selects ................................... 15
6.5 Array Selects ..................................................................... 15
6.6 Reading and Writing Arrays .............................................. 15
7.0 Module Instances ........................................................................ 16
8.0 Primitive Instances ..................................................................... 18
9.0 Generate Blocks ......................................................................... 20
10.0 Procedural Blocks ....................................................................... 22
10.1 Procedural Time Controls .................................................. 23
10.2 Sensitivity Lists ................................................................. 23
10.3 Procedural Assignment Statements ................................... 24
10.4 Procedural Programming Statements ................................ 25
11.0 Continuous Assignments ............................................................ 27
12.0 Operators .................................................................................... 28
13.0 Task Definitions ......................................................................... 30
14.0 Function Definitions ................................................................... 31
15.0 Specify Blocks ............................................................................ 32
15.1 Pin-to-pin Path Delays ....................................................... 32
15.2 Path Pulse (Glitch) Detection ............................................ 33
15.3 Timing Constraint Checks ................................................. 34
16.0 User Defined Primitives (UDPs) ................................................ 35
17.0 Common System Tasks and Functions ...................................... 37
18.0 Common Compiler Directives .................................................... 40
19.0 Configurations ............................................................................ 42
20.0 Synthesis Supported Constructs ................................................. 44 |
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