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This thesis by K. Esmark is about the investigation of ESD protection elements under typical ESD stress situations by means of TCAD tools
An ESD stress event is linked to high current densities and high temperature distributions, as an enormous amount of energy is deposited in a protection element on a very short time scale. On the one hand the focus of this work is to uncover weak spots of the physical models implemented in the device simulator with respect to their validity in the ESD relevant regime and to provide a calibration strategy to prepare TCAD tools for ESD devices simulation. On the other hand this work puts highlights on some very fundamental ESD results gained from 2-D/3-D device simulation. The thesis covers questions like "how to derive pre-Si ESD protection concepts?" and "how to estimate device failure thresholds under TLP or HBM stressing conditions as a consequence of thermal stress?". The part about 3-D device simulation deals with important issues like reasons for "inhomogeneous triggering" and "current filamentation".
Using the ggNMOS transistor as a test case, this thesis definitely shows how to make device simulation a predictive tool for ESD engineers to reduce and shorten development efforts and to understand device specific behavior under ESD stress conditions. |
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发表于 2008-5-26 12:54:50
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