【Newnes 2003】Demystifying Mixed Signal Test Methods (Demystifying Technology)

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Content for your reference:
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1 Failure Analysis and ESD 1
1.1 Introduction 1
1.1.1 FA Techniques for Evaluation of ESD Events 2
1.1.2 Fundamental Concepts of ESD FA Methods
and Practices 3
1.1.3 ESD Failure: Why Do Semiconductor Chips Fail? 4
1.1.4 How to Use FA to Design ESD Robust Technologies 5
1.1.5 How to Use FA to Design ESD Robust Circuits 6
1.1.6 How to Use FA for Temperature Prediction 7
1.1.7 How to Use Failure Models for Power Prediction 8
1.1.8 FA Methods, Design Rules, and ESD Ground Rules 9
1.1.9 FA and Semiconductor Process-Induced ESD Design
Asymmetry 9
1.1.10 FA Methodology and Electro-thermal Simulation 10
1.1.11 FA and ESD Testing Methodology 10
1.1.12 FA Methodology for Evaluation of ESD Parasitics 13
1.1.13 FA Methods and ESD Device Operation Verification 14
1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical
Connectivity 14
1.1.15 How to Use FA to Eliminate Failure Mechanisms 16
1.2 ESD Failure: How Do Micro-electronic Devices Fail? 16
1.2.1 ESD Failure: How Do Metallurgical Junctions Fail? 18
1.2.2 ESD Failure: How Do Insulators Fail? 18
1.2.3 ESD Failure: How Do Metals Fail? 19
1.3 Sensitivity of Semiconductor Components 20
1.3.1 ESD Sensitivity as a Function of Materials 20
1.3.2 ESD Sensitivity as a Function of Semiconductor Devices 21
1.3.3 ESD Sensitivity as a Function of Product Type 21
1.3.4 ESD and Technology Scaling 22
1.3.5 ESD Technology Roadmap 24
1.4 How Do Semiconductor Chips Fail—Are the Failures Random
or Systematic? 24
1.5 Closing Comments and Summary 26
Problems 26
References 27
2 Failure Analysis Tools, Models, and Physics of Failure 31
2.1 FA Techniques for Evaluation of ESD Events 31
2.2 FA Tools 34
2.2.1 Optical Microscope 34
2.2.2 Scanning Electron Microscope 35
2.2.3 Transmission Electron Microscope 35
2.2.4 Emission Microscope 35
2.2.5 Thermally Induced Voltage Alteration 36
2.2.6 Superconducting Quantum Interference Device Microscope 37
2.2.7 Atomic Force Microscope 38
2.2.8 The 2-D AFM 40
2.2.9 Picosecond Current Analysis Tool 40
2.2.10 Transmission Line Pulse—Picosecond Current Analysis Tool 42
2.3 ESD Simulation: ESD Pulse Models 43
2.3.1 Human Body Model 43
2.3.2 Machine Model 44
2.3.3 Cassette Model 45
2.3.4 Socketed Device Model 46
2.3.5 Charged Board Model 46
2.3.6 Cable Discharge Event 47
2.3.7 IEC System-Level Pulse Model 49
2.3.8 Human Metal Model 50
2.3.9 Transmission Line Pulse Testing 51
2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model 53
2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model 53
2.4 Electro-Thermal Physical Models 54
2.4.1 Tasca Model 54
2.4.2 Wunsch–Bell Model 56
2.4.3 Smith–Littau Model 60
2.4.4 Ash Model 62
2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko
Model 63
2.4.6 Dwyer, Franklin, and Campbell Model 63
2.4.7 Vlasov–Sinkevitch Model 67
2.5 Statistical Models for ESD Prediction 68
2.6 Closing Comments and Summary 70
Problems 70
References 71
3 CMOS Failure Mechanisms 77
3.1 Tables of CMOS ESD Failure Mechanisms 77
3.2 LOCOS Isolation-Defined CMOS 77
3.2.1 LOCOS-Bound Structures 82
3.2.2 LOCOS-Bound Pþ/N-well Junction Diode 83
3.2.3 LOCOS-Bound Nþ/P Substrate Junction Diode 84
3.2.4 LOCOS-Bound N-well/P Substrate Junction Diode 84
3.2.5 LOCOS-Bound Lateral N-well to N-well 85
3.2.6 LOCOS-Bound Lateral Nþ to N-well 85
3.2.7 LOCOS-Bound Lateral PNP Bipolar 85
3.2.8 LOCOS-Bound Thick Oxide MOSFET 85
3.3 Shallow Trench Isolation (STI) 86
3.3.1 STI Pull-down ESD Failure Mechanism 86
3.3.2 STI Pull-down and Gate Wrap-around 87
3.3.3 Silicides and Diodes 88
3.3.4 Non-silicide Diode Structures 88
3.3.5 STI-Defined Pþ/N-well Diode 88
3.3.6 STI-Defined N-well to Substrate Diode 88
3.3.7 STI Lateral N-well to N-well NPN Structures 90
3.4 Polysilicon-Defined Devices 90
3.4.1 Polysilicon-Bound Gated Diode 91
3.5 Lateral Diode with Block Mask 92
3.6 MOSFETs 92
3.6.1 N-channel MOSFETs 93
3.6.2 N-channel Multi-finger MOSFETs 95
3.6.3 Cascoded Series N-channel MOSFETs 97
3.6.4 P-channel MOSFETs 97
3.6.5 P-channel Multi-finger MOSFETs 98
3.6.6 Tungsten Silicide Gate MOSFET 98
3.6.7 Polysilicon Silicide Gate MOSFET 98
3.6.8 Metal Gate/High k Dielectric MOSFET 98
3.7 Resistors 99
3.7.1 Diffused Resistors 99
3.7.2 N-well Resistors 99
3.7.3 Buried Resistors 101
3.7.4 Silicide Blocked N-diffusion Resistors 102
3.8 Interconnects: Wires, Vias, and Contacts 102
3.8.1 Aluminum Interconnects 103
3.8.2 Copper Interconnects 104
3.8.3 Tungsten Interconnects 107
3.8.4 Vias 107
3.8.5 Contacts 110
3.9 ESD Failure in CMOS Nanostructures 112
3.9.1 ESD Failures in 130 nm Technology 112
3.9.2 ESD Failures in 90 nm Technology 113
3.9.3 ESD Failures in 65 nm Technology 114
3.9.4 ESD Failures in 45 nm Technology 115
3.9.5 ESD Failures in 32 nm Technology 115
3.9.6 ESD Failures in 22 nm Technology 116
3.10 Closing Comments and Summary 118
Problems 118
References 119
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bravexplorer

多谢楼主!

vincentlu

thanks!

mariobro

run test

szyacj

有英文版本，不知道这个翻译的质量怎么样

szyacj

正在找！！！！！！借了一本

sunjimmy

Good job

lilei751109

先下了,多谢楼主!

walking001

A nice book.