library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(
clk:in std_logic; --12M时钟信号
clk_scanut std_logic
);
end;
architecture abc of fenpin is
signal cnt:integer range 0 to 30;
begin
process(clk)
begin
if(rising_edge(clk))then
if(cnt=cnt'high)then
cnt<=0;
else
cnt<=cnt+1;
end if;
end if;
end process;
process(cnt,clk)
begin
if(rising_edge(clk))then
if(cnt>=cnt'high/2)then
clk_scan<='1';
else
clk_scan<='0';
end if;
end if;
end process;
end;