A NEW ARCHITECTURE FOR VOLTAGE-CONTROLLED OSCILLATOR_Phd论 文

kevinwjs

CHAPTER 1 INTRODUCTION.................................................................................1
1.1 Motivation.........................................................................................................1
1.2 Scope of Research.............................................................................................6
1.3 Thesis Organization...........................................................................................7
CHAPTER 2 OSCILLATOR PHASE NOISE............................................................9
2.1 Linear Time-Invariant Phase-Noise Model.....................................................11
2.2 Nonlinear Time-Varying Phase-Noise Model.................................................14
2.3 Linear Time-Varying Phase-Noise Model......................................................17
CHAPTER 3 INTEGRATED LC RESONATOR.....................................................22
3.1 On-chip Spiral Inductors.................................................................................24
3.1.1 Losses in Spiral Inductors.....................................................................25
3.1.2 Circuit Model of Spiral Inductors.........................................................28
3.2 On-chip Varactors...........................................................................................31
3.2.1 PN-Junction Varactors.........................................................................31
3.2.2 MOS Varactors.....................................................................................32
3.2.3 Three-Terminal MOS Varactors...........................................................34
CHAPTER 4 CROSS-COUPLED TRANSCONDUCTOR CMOS VCO................37
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4.1 Circuit Analysis...............................................................................................39
4.2 Phase Noise Analysis......................................................................................41
4.3 Phase Noise Reduction Techniques................................................................45
CHAPTER 5 A NEW LOW-PHASE-NOISE CMOS LC VCO................................53
5.1 Circuit Analysis...............................................................................................54
5.2 Phase Noise Analysis......................................................................................62
5.3 Design Procedure............................................................................................66
5.4 Design of a 5.5-GHz VCO..............................................................................73
5.4.1 Inductors...............................................................................................73
5.4.2 Output Buffer........................................................................................75
5.4.3 Startup Circuit......................................................................................76
5.4.4 Tuning Circuit.......................................................................................76
5.4.5 Main VCO Circuit.................................................................................77
CHAPTER 6 SIMULATION AND EXPERIMENTAL RESULTS.........................81
6.1 Simulation Methodology.................................................................................81
6.2 Simulation Results of the New VCO Design..................................................86
6.3 Simulation Result of a Reference VCO Design..............................................92
6.4 Experimental Results.......................................................................................94
6.4.1 Test Setup..............................................................................................94
6.4.2 Test of the Output Balun.......................................................................97
6.4.3 Test of the Tank Inductor......................................................................98
6.4.4 Test of the VCOs.................................................................................100
CHAPTER 7 CONCLUSIONS................................................................................108
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7.1 Low-Phase-Noise CMOS VCO.....................................................................108
7.2 Summary of Contributions............................................................................109
7.3 Future Works.................................................................................................109

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fanjx

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averyer

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zys0115

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