HV ESD protection-2

jian1712

Lateral DMOS design for ESD robustness

abstract
This paper presents the design of efficient ESD protection in lateral DMOS (LDMOS) power transistor. Using characterization of the LDMOS transistor under ESD conditions with various gate and drain clamps, the design for minimum power dissipation is established. The results show that for ESD regime of pulses the channel heating effects are minimum and that optimum ESD level can be achieved by driving the device into maximum possible MOS conduction. Based on these results, an empirical formula for effective ESD design is derived.
Lateral DMOS design for ESD robustness.pdf (361.25 KB , 下载次数: 204 )

2010-5-26 18:20 上传

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ESD protection solutions for high voltage technologies
http://www.eetop.cn/bbs/thread-254145-1-1.html
Other esd papers
http://www.eetop.cn/bbs/thread-254229-1-1.html

Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors
Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors.rar (1.72 MB , 下载次数: 246 )

2010-5-26 18:33 上传

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Ralphjh

谢谢分享

skahill

Helpful, thanks

qq114040540

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ni2121

谢谢，看一下

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