连续时间调制器运放等效负载

new_bird

                               
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请教一下大家 如果一个连续时间调制器 采样10MHZ 带宽24kHz 电路第一级的积分电容是12pF 第二级是6pF 那么在运放单独仿真增益、UGBW时，负载应该是多少呢

迷路大脸猫

第一个运放看到是自己的输入电容，就按首尾短接来仿，当然电容有寄生，可适当加点寄生电容到地

new_bird

   

迷路大脸猫 发表于 2025-5-31 14:34
第一个运放看到是自己的输入电容，就按首尾短接来仿，当然电容有寄生，可适当加点寄生电容到地 ...

感谢回答 按照这个去理解论文的运放较低就比较清楚了 正常一个CT 采样3M 第一级积分电容18P 两级运放增益70dB  单位增益带宽 18MHz 消耗50uA 实际的运放负载要小的多

IC_Li

这个积分电容要算做负载的一部分吧，感觉大部分论文里没算进去

new_bird

要算的

nanke

积分电容要算的呀，对于某些case还要按米勒电容乘以一个A(s)的倍数等效呢。

cykcbs

pavan 的understanding sigma delta adc书中是说A question that arises during the OTA design phase is – “What feedback factor should one use to analyze OTA stability?” In our modulator, the OTA forms part of the integrator, as shown in Figure 10.56(a). The parasitic input capacitance of the OTA, which is not negligible, is denoted by c . As we have seen earlier in this chapter, the unity-gain frequency of the integrator ( 1 RC) has to be much smaller than the unity-gain bandwidth of the OTA. Therefore, as far as the feedback loop enclosing the OTA is concerned, the integrating capacitors C can be treated as short-circuits at frequencies around the OTA’s unity-gain bandwidth, as shown in Figure 10.56(b). By a similar argument, the influence of the resistors on the loop-gain at high frequencies can be neglected. It is thus seen that the OTA should be stable in a unity-feedback configuration. The input parasitic capacitance c loads the second stage of the OTA. To determine loop-gain, the loop has to be conceptually broken to the right of c , as shown in Figure 10.56(b). To simulate the loop-gain, therefore, it is appropriate to use the setup shown in part (c) of the figure. In the design of Figure 10.55, c 0 5 pF.    我的理解是说运放设计带宽比1/RC大，所以积分电容在高频按照短路处理，然后说负载电容是输入寄生电容，但我很好奇有没有公式推导之类的