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本帖最后由 arasi16 于 2025-3-21 01:22 编辑
Dear IC-Design Family Members,
Myself having 20+ years IC Layout/Mask design (RF/Analog/AMS/IO/ESD/Logic for design like PLL, SERDES, DDRIO, PCIE, USB, ADC, DAC, BGR, OPAMP, CTLE, DFE, LNA, PA, RX, TX, Temperatue Sensor, Standard Cell, Special IO's, and etc.) with Full-chip/Tapeout experince, if any one looking for partener in this regards please let me know, we are based out in INDIA(Bengaluru). we will give free trail for two weeks in case you would like to know our capabilities.
Please feel free contact on my email ID : layoutmask@gmail.com
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