verilog编译出错

时间在走人在变

这是一个5位的超前进位加法器，17、18、21、22这四行一直报错，看了半天也没头绪，求大佬解惑

joshua2784920

It seems that the SystemVerilog compile option was not used. If that's the case, sum, pi, gi, and ci should be declared as reg, and pi and gi cannot be declared as reg and have their values assigned using assign.

时间在走人在变

忘了error贴上来，这里补一下，这四行报的错一模一样



Error (10170): Verilog HDL syntax error at test1.v(17) near text: "=";  expecting ".", or an identifier. Check for and fix any syntax errors that appear immediately before or at the specified keyword.

songzijian87

漏了always @*或者assign

时间在走人在变

我靠，这低级错误也能犯，我真的是无语，谢谢大佬指点！