VCS在sim时对异步复位同步释放的寄存器报hold的violation问题，谢谢

IC牛马

求助各位前辈，我的设计中由于时钟域很多，复位方式为异步复位同步释放，使用两级寄存器打拍，以其中一个为例，每个都一样，代码为
always @(posedge Clk_VF1 or negedge RstN_I) begin
   if(!RstN_I) begin
       RstN_S1        <= 1'b0;
       RstN_VF1 <= 1'b0;
   end else begin
       RstN_S1        <= 1'b1;
       RstN_VF1        <= RstN_S1;
   end
end

把VF1作为Clk_VF1时钟域下的复位端，我处理的思路是在DC阶段对二级寄存器的QN端进行set dont touch和set ideal network，如下：
set_dont_touch_network [get_pins T1/G1/D3/RstN_VF1_reg/QN] ;
set_ideal_network [get_pins T1/G1/D3/RstN_VF1_reg/QN] ;

然后在ICC2013后端place之前，解除ideal_network属性，以让后端按fanout去处理同步释放后的rst，指令如下
remove_ideal_network [get_pins T1_G1_D3_RstN_VF1_reg/QN] ;
最后做pt的时候也没有时序违例，也没有rec/rom的报错（进行了检查），另外对[get_pins T1/G1/D3/RstN_VF1_reg/QN] 也尝试过在DC中设置false path等，对结果也没影响，但是在vcs的sim阶段对异步复位同步释放的寄存器报了violation，如下：

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/verilog/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF1_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S1_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF2_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S2_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_SYNC_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 76 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_S1_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 487 );


"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF1_REG
    $hold( posedge CK:1205000000, posedge SN:1205000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S1_REG
    $hold( posedge CK:1205000000, posedge RN:1205000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF2_REG
    $hold( posedge CK:1205000000, posedge SN:1205000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S2_REG
    $hold( posedge CK:1205000000, posedge RN:1205000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_SYNC_REG
    $hold( posedge CK:1205000000, posedge SN:1205000000, limit: 76 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_S1_REG
    $hold( posedge CK:1205000000, posedge RN:1205000000, limit: 487 );

请问各位前辈这是我对异步复位同步释放的前后端处理方式不对么，还是由什么其它原因造成的，如果有不合适的地方应该如何修改我上面的指令。因为仿真跑出的结果某个信号在经历一次组合逻辑变化后变为不定态，由于服务器vcs软件环境问题原因无法使用show schematic等操作分析根源，所以怀疑是上面的原因导致，并且上面的警告也不让我放心，请教下前辈们，谢谢

gaurson

从后仿真角度看，XXX_RSTN_VF1_REG，同步操作的第一级触发器可以不用检查时序，整理到一个文件里面，通过-tfile传递给工具。

IC牛马

gaurson 发表于 2024-8-21 20:20
从后仿真角度看，XXX_RSTN_VF1_REG，同步操作的第一级触发器可以不用检查时序，整理到一个文件里面，通过-t ...

好的，谢谢！！后来查看确实也对后仿结果没有影响！