【求助】virtuoso layout DRC报错

ceciliayan

小白求助！

用finfet做INV的版图，在用virtuoso calibre DRC进行验证的时候出了好多报错，调整了布线之后整理了一下还有下面这些类型的error，想问问这些问题是啥意思，还有哪些是可以暂时忽略的（一些问题已经看了帮助文档解决了，剩下的还是不太理解）非常感谢！

SVT_N_R_8:

ALL_GTmust be covered by (SVT_N, SVT_P, LVT_N, LVT_P, ULVT_N, ULVT_P, HVT_N,
HVT_P，LPN_N,LPN_P), except INST, DSTR,DIPNP, VARMOS, DO, RESIV, RESP1, DMCNK1, MARKS, OCCD, OCOVL, RESP3t region for3t resistor bulk region

GT_S_17f:

Spacebetween ALL_GT(0.07um<=width<=0.16um and one side poly space >= 0.118um)and ALL_GT, except ESDI01, ESDI02 and OCOVL regions = 0.118, 0. 119um

GT_L_7:

Lengthof (( ALL_GT(width>=0.032um) not ALL_P2) INTERACT ALL_AA), except DMPNP,VARMOS, and DMC1 regions <= 0,16um

GT_R_10:

(((ALL_GTNOT P2) NOT (DUM_GT INSIDE DMCB1)) CUT (DO OR ((DMPNP OR DSTR) OR VARMOS))) isnot allowed

GT_R_14:

ALL_GTmust be fully covered by (SN or SP), except DMONK1, RESNW, MARKS and OCOVLregions

SN_W_1:

SNwidth, except INST regions >= 0.192um

SN_A_1a:

SNareas, except INST region >= 0.087um²

MOG_L_1:

AOP_MOG(width = 0.04um) length, except INST region = 0.102~0.33um

M1_S_1:

Spacebetween two M1s, except LOHO region, >= 0.032um

M1_A_1:

M1area, except INST region >= 0.0061um²

M1_A_3：

M1area when all of edge lengths < 0.081um, except a M1 filling 0.077um*0.077umrectangular pattern

LU_5_G_NMOS：

Spacefrom any point within the S/D region to the nearest pickup AA region insidesthe same well for I/O and internal circuits, except OCCDFH region <= 50um

이지은

？？？你都打出来了，翻译一下不就是答案么？

이지은

该覆盖的没盖全，width不满足，面积不满足，space不满足，latch up。

ceciliayan

이지은 发表于 2024-3-4 10:13
该覆盖的没盖全，width不满足，面积不满足，space不满足，latch up。

收到，感谢