A 2–1600-MHz CMOS Clock Recovery

jswon

A general-purpose phase-locked loop (PLL) with
programmable bit rates is presented demonstrating that large
frequency tuning range, large power supply range, and low jitter
can be achieved simultaneously. The clock recovery architecture
A 2–1600-MHz CMOS Clock Recovery PLL with Low- Capability

uses phase selection for automatic initial frequency capture. The
large period jitter of conventional phase selection is eliminated
through feedback phase selection. Digital control sequencing of
the feedback enables accurate phase interpolation without the
traditional need of analog circuitry. Circuit techniques enabling
low-V dd operation of a PLL with differential delay stages are
presented. Measurements show a PLL frequency range of 1–200
MHz at V dd = 1:2 V linearly increasing to 2–1600 MHz at V dd
= 2:5 V, achieved in a standard process technology without low
threshold voltage devices. Correct operation has been verified
down to V dd = 0:9 V, but the lower limit of differential operatio

leonken163

thanksc8

fanjx

paper 哎呀

opqfeixue

xie xie le

microuser

thanks!!

JJmeow

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