Hspice仿真避坑--VA created an intermediate Bad C code from Verilog-A module

nihao_ya

今天仿真时发现一个问题，原来在另一个文件夹的sp文件突然跑不了了，网上也没找到解决方法，仔细检查发现是文件的目录问题，文件目录不能带中文！！！

仿真时的lis文件如下：


****** HSPICE -- O-2018.09-SP2 win64 (Feb 25 2019) ******                     
  Copyright (c) 1986 - 2020 by Synopsys, Inc. All Rights Reserved.              
  This software and the associated documentation are proprietary
  to Synopsys, Inc. This software may only be used in accordance
  with the terms and conditions of a written license agreement with
  Synopsys, Inc. All other use, reproduction, or distribution of
  this software is strictly prohibited.
  Input File: Inverter.sp                                                      
  Command line options: C:\synopsys\Hspice_O-2018.09-SP2\WIN64\hspice.com -i Inverter.sp -o D:\TFT模型\Inverter.lis
  Start time: Tue Oct 27 17:14:49 2020
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**info** *pvaI* Module (ntft): 3 unexpanded port, 0 init, 15 behav, 4 contrib, 25/11 expr(s)

**info** *pvaI*        No DIS, 0/0 afCount, 0 MT, sys, IO(0/0/0/0)

**info** *pvaI*        0 gmdIsThreadSafe

**info** *pvaI*        0 const-G and 0 const-C, Has switchBranch, 22 bypassOpt, 0 bus2scalar, 0 vwb

**info** *pvaI*        set_va_exp = 80 [80.0, 704.0] set by default

**warning** *pvaW*        variable 'vg' initialized but not used in RHS, deleted (NTFT.va:30)

**warning** *pvaW*                   To relax this rule, use 'setenv PVA_KEEP_VARS 1' to keep variables for probing.

**warning** *pvaW*        variable 'vgd' declared but not used in RHS, deleted (NTFT.va:22)

**info** *pvaI*        generated 0 flow node(s) during compilation.

**info** *pvaI* Module (ptft): 3 unexpanded port, 0 init, 15 behav, 4 contrib, 25/11 expr(s)

**info** *pvaI*        No DIS, 0/0 afCount, 0 MT, sys, IO(0/0/0/0)

**info** *pvaI*        0 gmdIsThreadSafe

**info** *pvaI*        0 const-G and 0 const-C, Has switchBranch, 22 bypassOpt, 0 bus2scalar, 0 vwb

**info** *pvaI*        set_va_exp = 80 [80.0, 704.0] set by default

**warning** *pvaW*        variable 'vg' initialized but not used in RHS, deleted (PTFT.va:30)

**warning** *pvaW*        variable 'vgd' declared but not used in RHS, deleted (PTFT.va:22)

**info** *pvaI*        generated 0 flow node(s) during compilation.

**info** *pvaI* #### Total 454 line-size(s), 50/22 expr(s), 8 contr(s), 0 init(s), 30 behav(s), 6 port(s)

**info** *pvaI* system & gcc return code is 1

**error** *pvaE* pVA created an intermediate Bad C code from Verilog-A module



          ***** job aborted
1****** HSPICE -- O-2018.09-SP2 win64 (Feb 25 2019) ******                     
******  


****** job statistics summary tnom=  25.000 temp=  25.000 ******

  ******  HSPICE Threads Information  ******

  Command Line Threads Count :     1
  Available CPU Count        :     4
  Actual Threads Count       :     1


  ******  Circuit Statistics  ******
  # nodes       =       0 # elements   =       0
  # resistors   =       0 # capacitors =       0 # inductors   =       0
  # mutual_inds =       0 # vccs       =       0 # vcvs        =       0
  # cccs        =       0 # ccvs       =       0 # volt_srcs   =       0
  # curr_srcs   =       0 # diodes     =       0 # bjts        =       0
  # jfets       =       0 # mosfets    =       0 # U elements  =       0
  # T elements  =       0 # W elements =       0 # B elements  =       0
  # S elements  =       0 # P elements =       0 # va device   =       0
  # vector_srcs =       0 # N elements =       0


  ******  Runtime Statistics (seconds)  ******

  analysis           time    # points   tot. iter  conv.iter
  op point           0.00           1           0
  readin             0.01
  errchk             0.00
  setup              0.00
  output             0.00


           peak memory used         57.13 megabytes
           total cpu time            4.05 seconds
           total elapsed time        4.30 seconds
           job started at     17:14:49 10/27/2020
           job ended   at     17:14:53 10/27/2020


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