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一、资料1：人工智能芯片技术白皮书（2018）
资料来源：清华大学北京未来芯片技术高精尖创新中心
主要内容：
（1）AI芯片的关键特征
（2）AI芯片发展现状
（3）AI芯片的技术挑战
（4）AI芯片架构设计趋势
（5）AI芯片中的存储技术
（6）新兴计算技术
（7）神经形态芯片
二、资料2：FPL国际会议论文（2017）
会议论文
PDF清单：
● Ivo Bolsens:
"All programmable FPGA, providing hardware efficiency to software programmers".1-3
● Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka:
01Evaluating high-level design strategies on FPGAs for high-performance computing.1-4
● Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar:
02Toward a pixel-parallel architecture for graph cuts inference on FPGA.1-4
● Mohammad Hosseinabady, José Luis Núñez-Yáñez:
03A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.1-4
● Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron, Mircea Stan:
04REAPR: Reconfigurable engine for automata processing.1-8
● Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka:
05Evaluating high-level design strategies on FPGAs for high-performance computing.1-4
● Ryan A. Cooke, Suhaib A. Fahmy:
06In-network online data analytics with FPGAs.1-2
● Pedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens:
07Area-optimized montgomery multiplication on IGLOO 2 FPGAs.1-4
● Jinnan Ding, Shuguo Li:
08Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition.1-4
● Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio:
09Optimizing streaming stencil time-step designs via FPGA floorplanning.1-4
● Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato:
10A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA.1
● Eric Matthews, Lesley Shannon:
11TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features.1-4
● Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat:
12ARMHEx: A hardware extension for DIFT on ARM-based SoCs.1-7
● Michal Kekely, Jan Korenek:
13Mapping of P4 match action tables to FPGA.1-2
● Jinnan Ding, Shuguo Li:
14Broken-Karatsuba multiplication and its application to Montgomery modular multiplication.1-4
● Hongyuan Ding, Miaoqing Huang:
15PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system.1-8
● Hiroki Nakahara, Tomoya Fujii, Shimpei Sato:
16A fully connected layer elimination for a binarizec convolutional neural network on an FPGA.1-4
● Brice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, Viktor Fischer:
17Complete activation scheme for FPGA-oriented IP cores design protection.1
● Size Xiao, Neil Bergmann, Adam Postula:
18Parallel RRT∗ architecture design for motion planning.1-4
● Ioannis Parnassos, Nikolaos Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Athanasios Gkaras, Konstantinos Kanellis, Christos D. Antonopoulos, Michalis Spyrou, Manolis Maroudas:
19A programming model and runtime system for approximation-aware heterogeneous computing.1-4
● Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang:
20PAAS: A system level simulator for heterogeneous computing architectures.1-8
● Bruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi:
21A partial reconfiguration based microphone array network emulator.1-4
● Kizhepatt Vipin, Jan Gray, Nachiket Kapre:
22Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs.1-8
● Mitra Purandare, Raphael Polig, Christoph Hagleitner:
23Accelerated analysis of Boolean gene regulatory networks.1-6
● Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk:
24F-C3D: FPGA-based 3-dimensional convolutional neural network.1-4
● Vladimir Rozic, Bohan Yang, Jo Vliegen, Nele Mentens, Ingrid Verbauwhede:
25The Monte Carlo PUF.1-6
● Gaël Deest, Tomofumi Yuki, Sanjay Rajopadhye, Steven Derrien:
26One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs.1-8
● Mirjana Stojilovic:
27Parallel FPGA routing: Survey and challenges.1-8
● Yehya Nasser, Jean-Christophe Prévotet, M. Heiard, Jordane Lorandel:
28Dynamic power estimation based on switching activity propagation.1-2
● Muhsen Owaida, Hantian Zhang, Ce Zhang, Gustavo Alonso:
29Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms.1-8
● Kevin Nam, Blair Fort, Stephen Dean Brown:
30FISH: Linux system calls for FPGA accelerators.1-4
● Benedikt Janßen, Pascal Zimprich, Michael Hübner:
31A dynamic partial reconfigurable overlay concept for PYNQ.1-4
● Yanzhe Li, Kai Huang, Luc Claesen:
32High-quality view interpolation based on depth maps and its hardware implementation.1-6
● Stelios Mavridis, Emmanouil Pavlidakis, Ioannis Stamoulias, Christos Kozanitis, Nikolaos Chrysos, Christoforos Kachris, Dimitrios Soudris, Angelos Bilas:
33VineTalk: Simplifying software access and sharing of FPGAs in datacenters.1-4
● Shengjia Shao, Wayne Luk:
34Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation.1-6
● Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow:
35Heterogeneous virtualized network function framework for the data center.1-8
● Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang, Yong Chen:
36OpenSoC system architect: An open toolkit for building soft-cores on FPGAs.1
● Yohann Uguen, Florent de Dinechin, Steven Derrien:
37Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations.1-8
● James Stanley Targett, Peter D. Düben, Wayne Luk:
38Validating optimisations for chaotic simulations.1-4
● Ephrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho:
39A high-throughput reconfigurable processing array for neural networks.1-4
● Alexander Wild, Georg T. Becker, Tim Güneysu:
40A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs.1-7
● Christos Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos:
41A generic high throughput architecture for stream processing.1-5
● Mario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard:
42Transparent memory encryption and authentication.1-6
● Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
43Reliable SEU monitoring and recovery using a programmable configuration controller.1-6
● Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat:
44ARMHEx: A framework for efficient DIFT in real-world SoCs.1
● Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton:
45Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.1-4
● Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch:
46Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation.1-8
● Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
47In-switch approximate processing: Delayed tasks management for MapReduce applications.1-4
● Lijuan Li, Shuguo Li:
48High throughput AES encryption/decryption with efficient reordering and merging techniques.1-4
● Nachiket Kapre:
49Deflection-routed butterfly fat trees on FPGAs.1-8
● Stephan Nolting, Lin Liu, Guillermo Payá Vayá:
50Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices.1-4
● Jose Raul Garcia Ordaz, Dirk Koch:
51Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit.1-4
● Sadegh Yazdanshenas, Vaughn Betz:
52Quantifying and mitigating the costs of FPGA virtualization.1-7
● William Diehl, Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj:
53Comparison of hardware and software implementations of selected lightweight block ciphers.1-4
● Thomas Townsend, Brent E. Nelson:
54Vivado design interface: An export/import capability for Vivado FPGA designs.1-7
● Junyi Liu, John Wickerson, George A. Constantinides:
55Tile size selection for optimized memory reuse in high-level synthesis.1-8
● Umar Afzaal, Jeong-A Lee:
56FPGA-based design of a self-checking TMR voter.1-4
● Nikolaos Alachiotis, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos:
57Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study.1-4
● Ryouhei Maeda, Tsutomu Maruyama:
58An implementation method of poisson image editing on FPGA.1-6
● Dimitrios Bozikas, Nikolaos Alachiotis, Pavlos Pavlidis, Euripides Sotiriades, Apostolos Dollas:
59Deploying FPGAs to future-proof genome-wide analyses based on linkage disequilibrium.1-8
● Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris:
60FPGA acceleration of spark applications in a Pynq cluster.1
● Yifeng Mo, Shuguo Li:
61Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs.1-6
● Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch:
62A security library for FPGA interlays.1-4
● Adewale Adetomi, Godwin Enemali, Tughrul Arslan:
63Relocation-aware communication network for circuits on Xilinx FPGAs.1-7
● Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz:
64Find the real speed limit: FPGA CAD for chip-specific application delay measurement.1-8
● Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang:
65Accelerating low bit-width convolutional neural networks with embedded FPGA.1-4
● Shuangnan Liu, Benjamin Carrión Schäfer:
66Learning-based interconnect-aware dataflow accelerator optimization.1-7
● Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser:
67FPGA modeling techniques for detecting and demodulating multiple wireless protocols.1-4
● Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:
68High performance binary neural networks on the Xeon+FPGA™ platform.1-4
● Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
69An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.1-8
● R. Aggleton, L. Ardila-Perez, F. A. Ball, Matthias Norbert Balzer, J. Brooke, L. Calligaris, M. Caselle, D. Cieri, E. J. Clement, G. Hall, K. Harder, P. R. Hobson, G. M. Iles, T. James, K. Manolopoulos, T. Matsushita, A. D. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. D. Reid, A. W. Rose, Oliver Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. P. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber:
70A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN.1-4
● Grace Zgheib, Paolo Ienne:
71Evaluating FPGA clusters under wide ranges of design parameters.1-8
● Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello:
72Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.1-4
● Stylianos I. Venieris, Christos-Savvas Bouganis:
73Latency-driven design for FPGA-based convolutional neural networks.1-8
● Simon Joel Schmidt, David Boland:
74Dynamic bitwidth assignment for efficient dot products.1-8
● David J. Greaves:
75Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo.1
● Konstantinos Boikos, Christos-Savvas Bouganis:
76A high-performance system-on-chip architecture for direct tracking for SLAM.1-7
● Zhe Lin, Wei Zhang, Sharad Sinha:
77Decision tree based hardware power monitoring for run time dynamic power management in FPGA.1-8
● Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen:
78High-performance video content recognition with long-term recurrent convolutional network for FPGA.1-4
● Thomas B. Preußer:
79Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs.1-7
● Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely:
80Line rate programmable packet processing in 100Gb networks.1
● Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá:
81Application-specific soft-core vector processor for advanced driver assistance systems.1-2
● Subho S. Banerjee, Mohamed El-Hadedy, Ching Y. Tan, Zbigniew T. Kalbarczyk, Steven S. Lumetta, Ravishankar K. Iyer:
82On accelerating pair-HMM computations in programmable hardware.1-8
● Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:
83Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts.1-8
● Henry Block, Tsutomu Maruyama:
84An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization.1-8
● Dennis R. E. Gnad, Fabian Oboril, Mehdi Baradaran Tahoori:
85Voltage drop-based fault attacks on FPGAs using valid bitstreams.1-7
● Yu Ting Chen, Jason Helge Anderson:
86Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software.1-8
● James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
87STRIPE: Signal selection for runtime power estimation.1-8
● ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, ChongYang Zeng, Jie Jin, Bin Li:
88An implementation of list successive cancellation decoder with large list size for polar codes.1-4
● Tobias Kenter, Jens Förstner, Christian Plessl:
89Flexible FPGA design for FDTD using OpenCL.1-7
● Brad L. Hutchings, Michael J. Wirthlin:
90Rapid implementation of a partially reconfigurable video system with PYNQ.1-8
● Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano:
91Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA.1-4
● Lester Kalms, Diana Göhringer:
92Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs.1-4
● Festus Hategekimana, Taylor J. L. Whitaker, Md Jubaer Hossain Pantho, Christophe Bobda:
93Shielding non-trusted IPs in SoCs.1-4
● Julian Caba, Fernando Rincón, Julio Dondo Gazzano:
94Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks.1-2
● Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy:
95Scalable high-performance architecture for convolutional ternary neural networks on FPGA.1-7
● Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
96Body bias optimization for variable pipelined CGRA.1-4
● Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li:
97Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.1-4
● Jiayi Sheng, Chen Yang, Ahmed Sanaullah, Michael Papamichael, Adrian M. Caulfield, Martin C. Herbordt:
98HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics.1-4
● João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
99K-means clustering on CGRA.1-4
● Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
100FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.1
● Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond:
101FPGA acceleration of multilevel ORB feature extraction for computer vision.1-8
● Bruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi:
102Demonstration of a partial reconfiguration based microphone array network emulator.1
● Oron Port, Yoav Etsion:
103DFiant: A dataflow hardware description language.1-4
● Wei Yan, Chenglu Jin, Fatemeh Tehranipoor, John A. Chandy:
104Phase calibrated ring oscillator PUF design and implementation on FPGAs.1-8
● John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan, Timothy Sherwood:
105A pythonic approach for rapid hardware prototyping and instrumentation.1-7
● Jin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang:
106FPGA acceleration of the scoring process of X!TANDEM for protein identification.1-4
● Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang:
107Exploring the potential of reconfigurable platforms for order book update.1-8
● Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
108Parallel dot-products for deep learning on FPGA.1-4
● David Sidler, Muhsen Owaida, Zsolt István, Kaan Kara, Gustavo Alonso:
109doppioDB: A hardware accelerated database.1
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发表于 2019-10-2 12:27:00
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