帮我看看这个！

fanxg88

ngdbuild -p xc95108-15-pc84 -uc p_raster.ucf -dd .. c:\xilinx\active\projects\p_raster\p_raster.edn p_raster.ngd
Release 4.1i - ngdbuild E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Command Line: ngdbuild -p xc95108-15-pc84 -uc p_raster.ucf -dd ..
c:\xilinx\active\projects\p_raster\p_raster.edn p_raster.ngd
Launcher: Executing edif2ngd "c:\xilinx\active\projects\p_raster\p_raster.edn"
"c:\xilinx\active\projects\p_raster\xproj\ver1\p_raster.ngo"
INFO:NgdBuild - Release 4.1i - edif2ngd E.30
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/xilinx/active/projects/p_raster/xproj/ver1/p_raster.ngo"...
Reading NGO file "c:/xilinx/active/projects/p_raster/xproj/ver1/p_raster.ngo"
...
Reading component libraries for design expansion...
Launcher: "R_SY_D_FF.ngo" is up to date.
Loading design module
"c:\xilinx\active\projects\p_raster\xproj\ver1\R_SY_D_FF.ngo"...
Launcher: "BUF_SEL.ngo" is up to date.
Loading design module
"c:\xilinx\active\projects\p_raster\xproj\ver1\BUF_SEL.ngo"...
Launcher: "INHB.ngo" is up to date.
Loading design module
"c:\xilinx\active\projects\p_raster\xproj\ver1\INHB.ngo"...
Launcher: Executing edif2ngd -noa "c:\xilinx\active\projects\p_raster\R_TFF.edf"
"c:\xilinx\active\projects\p_raster\xproj\ver1\R_TFF.ngo"
INFO:NgdBuild - Release 4.1i - edif2ngd E.30
INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Writing the design to
"c:/xilinx/active/projects/p_raster/xproj/ver1/R_TFF.ngo"...
Loading design module
"c:\xilinx\active\projects\p_raster\xproj\ver1\R_TFF.ngo"...
Annotating constraints to design from file "p_raster.ucf" ...
Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'U35/U7/B0' has no load
WARNING:NgdBuild:454 - logical net 'U35/U7/C0' has no load
NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2
Writing NGD file "p_raster.ngd" ...
Writing NGDBUILD log file "p_raster.bld"...
NGDBUILD done.
==================================================
hitop -f p_raster.ngd -d p_raster -s -l p_raster.log -o p_raster
Release 4.1i - Optimizer/Partitioner E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Considering device XC95108-PC84.
Flattening design..
Multi-level logic optimization...
Timing optimization...............................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 90 equations into 6 function blocks................................ERROR:Cpld - Cannot place signal Q<6>. Consider reducing the collapsing input
   limit or the product term limit to prevent the fitter from creating high
   input and/or high product term functions.
See the fitter report for details.
..
ERROR:Cpld - Cannot fit the design into any of the specified devices with the
   selected implementation options.
PROGRAM ABNORMALLY TERMINATED
==================================================
hitop -f p_raster.ngd -d p_raster -s -l p_raster.log -o p_raster
Release 4.1i - Optimizer/Partitioner E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Considering device XC95108-PC84.
Flattening design..
Multi-level logic optimization...
Timing optimization...............................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 90 equations into 6 function blocks................................ERROR:Cpld - Cannot place signal Q<6>. Consider reducing the collapsing input
   limit or the product term limit to prevent the fitter from creating high
   input and/or high product term functions.
See the fitter report for details.
..
ERROR:Cpld - Cannot fit the design into any of the specified devices with the
   selected implementation options.
PROGRAM ABNORMALLY TERMINATED

fanxg88

请帮我看看这个错误是怎么回事！！

jackzhang

你先不要选定108,也不要做ucf，是这自动fit一下，要不就选144在试试

CliffZhang

> ERROR:Cpld - Cannot place signal Q<6>. Consider reducing the collapsing input
看看这个吧？
应该是管脚不够了吧？