Low Power Methodology Manual For System-on-chip Design

virsim

thanks

jjww110

2008年的古董？

lujunfeng111

请楼主注明材料的时间，技术更新快，太老的资料没有参考价值。

kk2009

这本书是2008年出的，主要是讲解ARM和synospys合作研究出来的flow。

1 Introduction....................................................................................1
1.1 Overview ....................................................................................................... 1
1.2 Scope of the Problem..................................................................................... 2
1.3 Power vs. Energy........................................................................................... 3
1.4 Dynamic Power ............................................................................................. 4
1.5 The Conflict Between Dynamic and Static Power ........................................ 7
1.6 Static Power................................................................................................... 8
1.7 Purpose of This Book .................................................................................. 10
2 Standard Low Power Methods ...................................................13
2.1 Clock Gating................................................................................................ 13
2.2 Gate Level Power Optimization .................................................................. 15
2.3 Multi VDD................................................................................................... 16
2.4 Multi-Threshold Logic ................................................................................ 17
2.5 Summary of the Impact of Standard Low Power Techniques..................... 19
3 Multi-Voltage Design ...................................................................21
3.1 Challenges in Multi-Voltage Designs.......................................................... 22
3.2 Voltage Scaling Interfaces – Level Shifters................................................. 22
3.2.1 Unidirectional Level Shifters ......................................................... 23
3.2.2
3.2.3
3.2.4
3.2.5 Automation and Level Shifters....................................................... 27
3.2.6 Level Shifter Recommendations and Pitfalls ................................. 28
3.3 Timing Issues in Multi-Voltage Designs ..................................................... 29
3.3.1 Clocks............................................................................................. 29
3.3.2 Static Timing Analysis ................................................................... 30
3.4 Power Planning for Multi-Voltage Design .................................................. 30
3.5 System Design Issues with Multi-Voltage Designs..................................... 31
4 Power Gating Overview ..............................................................33
4.1 Dynamic and Leakage power profiles......................................................... 33
4.2
4.3 Principles of Power Gating Design ............................................................ 37
4.3.1 Power Switching – Fine Grain vs. Coarse Grain............................ 38
4.3.2 The Challenges of Power Gating.................................................... 39
5 Designing Power Gating..............................................................41
5.1 Switching Fabric Design ............................................................................. 42
5.1.1 Controlling the Switching Fabric ................................................... 44
5.1.2
5.2
5.2.1 Signal Isolation techniques............................................................. 45
5.2.2 Output or Input Isolation ................................................................ 47
5.2.3 Interface Protocols and Isolation .................................................... 48
5.2.4 Recommendations and Pitfalls for Isolation................................... 50
5.3
5.3.1 State Retention Using Scan Chains ................................................ 51
5.3.2 Retention Registers......................................................................... 54
5.3.3 Power Controller Design for Retention.......................................... 56
5.3.4 Partial vs. Full State Retention ....................................................... 56
5.3.5 System Level Issues and Retention ................................................ 58
5.3.6
5.4
5.4.1
5.4.2 Handshake Protocols ...................................................................... 61
5.4.3
5.5
Level Shifters – High to Low Voltage Translation......................... 23
Level Shifters – Low-to-High Voltage........................................... 24
Level Shifter Placement ................................................................. 25
Impact of Power Gating on Classes of Sub-systems................................... 36
Recommendations and Pitfalls for Power Gating Control ............. 44
Signal Isolation .......................................................................................... 45
State Retention and Restoration Methods ................................................... 50
Recommendations and Pitfalls for State Retention ........................ 58
Power Gating Control.................................................................................. 59
Power Control Sequencing.............................................................. 60
Recommendations and Pitfalls for Power Gating Controllers ....... 63
Power Gating Design Verification – RTL Simulation................................. 63
5.5.1 Inferring Power Gating Behavior in RTL....................................... 64
5.5.2 Inferring Power Gating and Retention Behavior in RTL ............... 68
5.6 Design For Test considerations ................................................................... 70
5.6.1 Power Gating Controls ................................................................... 70
5.6.2 Power Limitations during Scan Test............................................... 71
5.6.3 Testing the Switching Network ...................................................... 71
5.6.4 Testing Isolation and Retention ...................................................... 72
5.6.5 Testing the Power Gating Controller.............................................. 73
6 Architectural Issues for Power Gating ......................................75
6.1 Hierarchy and Power Gating ....................................................................... 75
6.2
6.2.1
6.2.2
6.3 Power State Tables and Always On Regions............................................... 82
7 A Power Gating Example............................................................85
7.1 Leakage Modes Supported .......................................................................... 85
7.2 Design partitioning ...................................................................................... 88
7.3 Isolation ....................................................................................................... 92
7.4 Retention...................................................................................................... 94
7.5 Inferring Power Gating and Retention ....................................................... 95
7.6 Measurements and Analysis........................................................................ 96
8 IP Design for Low Power ..........................................................101
8.1 Architecture and Partitioning for Power Gating........................................ 102
8.1.1 How and When to Shut Down...................................................... 103
8.1.2 What to Shut Down and What to Keep Alive .............................. 103
8.2 Power Controller Design for the USB OTG.............................................. 105
8.3 Issues in Designing Portable Power Controllers ....................................... 108
8.4 Clocks and Resets ..................................................................................... 109
8.5 Verification ................................................................................................ 109
8.6 Packaging IP for Reuse with Power Intent.................................................110
8.7 UPF for the USB OTG Core ......................................................................111
8.8 USB OTG Power Gating Controller State Machine...................................114

9 Frequency and Voltage Scaling Design ....................................121
9.1 Dynamic Power and Energy...................................................................... 122
9.2 Voltage Scaling Approaches...................................................................... 125
9.3 Dynamic Voltage and Frequency Scaling (DVFS).................................... 125
9.4 CPU Subsystem Design Issues.................................................................. 129
9.5 Adaptive Voltage Scaling (AVS) ............................................................... 130
9.6 Level Shifters and Isolation....................................................................... 131
9.7 Voltage Scaling Interfaces – Effect on Synchronous Timing.................... 132
9.8
10 Examples of Voltage and Frequency Scaling Design ............139
10.1 Voltage Scaling - A Worked Example for UMC 130nm ........................... 139
10.1.1 ULTRA926 System Design Block Diagram ................................ 140
10.1.2
10.1.3 Synchronous Design Constraints.................................................. 144
10.1.4 Simulated (predicted) Energy Savings Analysis .......................... 145
10.1.5
10.1.6
10.2.1
10.2.2
10.2.3
11 Implementing Multi-Voltage, Power Gated Designs.............155
11.1 Design Partitioning.................................................................................... 158
11.1.1 Logical and Physical Hierarchy.................................................... 158
11.1.2 Critical Path Timing ..................................................................... 160
11.2 Design Flow Overview.............................................................................. 160
11.3 Synthesis.................................................................................................... 162
11.3.1 Power Intent ................................................................................. 162
11.3.2 Defining Power Domains and Power Connectivity...................... 162
11.3.3 Isolation Cell Insertion ................................................................. 163
11.3.4 Retention Register Insertion ......................................................... 164
11.3.5 Level Shifter Insertion.................................................................. 166
11.3.6 Scan Synthesis.............................................................................. 168
11.3.7 Always-On Network Synthesis .................................................... 170
11.4 Multi Corner Multi Mode Optimization with Voltage Scaling Designs.... 171
11.5 Design Planning......................................................................................... 173
Control of Voltage Scaling ......................................................................... 136
Voltage/Frequency Range Exploration......................................... 141
Silicon-Measured Power and Performance Analysis................... 145
Silicon-Measured ULTRA926 DVFS Energy Savings Analysis .. 147
10.2 Voltage Scaling – A worked Example for TSMC 65nm........................... 150
Voltage/Frequency Range Exploration......................................... 151
Silicon-Measured Power and Performance Analysis.................... 151
ATLAS926 Case Study ................................................................. 150
11.5.1 Creating Voltage Areas................................................................. 173
11.5.2 Power Gating Topologies ............................................................. 175
11.5.3 In-rush Current Management ....................................................... 176
11.5.4 Recommendations: ....................................................................... 176
11.6 Power Planning.......................................................................................... 177
11.6.1 Decoupling Capacitor Insertion.................................................... 179
11.7 Clock Tree Synthesis................................................................................. 180
11.8 Power Analysis.......................................................................................... 183
11.9 Timing Analysis ........................................................................................ 184
11.10Low Power Validation............................................................................... 185
11.11Manufacturing Test.................................................................................... 185
12 Physical Libraries ....................................................................187
12.1 Standard Cell Libraries.............................................................................. 187
12.1.1 Modeling of Standard Cell Libraries............................................ 188
12.1.2 Characterization of Standard Cell Libraries ................................. 189
12.2 Special Cells - Isolation Cells.................................................................... 190
12.2.1
12.2.2 Output Isolation vs. Input Isolation ............................................. 193
12.2.3
12.2.4 Recommendations ........................................................................ 194
12.3 Special Cells - Level Shifters .................................................................... 195
12.4 Memories................................................................................................... 198
12.4.1 RAMs for Multi-Voltage Power Gated Designs........................... 199
12.4.2 Memories and Retention............................................................... 200
12.5 Power Gating Strategies and Structures .................................................... 200
12.5.1 Power Gating Structures............................................................... 201
12.5.2 Recommendations – Coarse Grain vs. Fine Grain ....................... 204
12.6 Power Gating Cells.................................................................................... 204
13 Retention Register Design .......................................................209
13.1 Retention Registers.................................................................................... 209
13.1.1 Single Pin “Live Slave” Retention Registers ............................... 209
13.1.2
13.1.3
13.1.4 Retention Register: Relative layout.............................................. 218
13.2.1
Signal Isolation............................................................................. 191
Sneak DC Leakage Paths .............................................................. 193
12.7 Power Gated Standard Cell Libraries ........................................................ 206
Dual Control Signal “Balloon” Retention Register ..................... 212
Single Control Signal “Balloon” Retention Register.................... 215
13.2 Memory Retention Methods....................................................................... 219
VDD Retention Method ................................................................. 219
13.2.2
13.2.3
13.2.4
14 Design of the Power Switching Network................................225
14.1 Ring vs. Grid Style ................................................................................... 225
14.1.1
14.1.2
14.1.3 Row and Column Grids................................................................ 229
14.1.4
14.1.5 Recommendations - Ring vs. Grid Style ..................................... 231
14.2 Header vs. Footer Switch .......................................................................... 232
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.3.1
14.3.2
14.3.3 Recommendations for Supply Distribution .................................. 239
14.4 A Sleep Transistor Example...................................................................... 239
14.5 Wakeup Current and Latency Control Methods........................................ 240
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8 Recommendations for Power Switching Control......................... 245
14.6 An Example of a Dual Daisy Chain Sleep Transistor Implementation..... 246
APPENDIX A Sleep Transistor Design.......................................249
A.1
A.1.1
A.1.2
A.1.3
A.1.4
Retention Latency Reduction Methods ........................................ 222
Source Biasing Method ................................................................. 221
Source-diode Biasing Method ...................................................... 219
Ring Style Implementation........................................................... 226
Grid Style Implementation ........................................................... 227
Hybrid Style Implementation ........................................................ 231
Switch Efficiency Considerations................................................. 232
Recommendations – Header vs. Footer........................................ 235
System Level Design Consideration.............................................. 235
Area Efficiency Consideration and L/W Choice .......................... 234
Body Bias Considerations............................................................. 235
Single Daisy chain sleep transistor distribution ........................... 241
Dual Daisy chain sleep transistor distribution............................... 241
Main Chain Turn-on Control ....................................................... 243
Buffer Delay Based Main Chain Turn-on Control ...................... 243
Parallel Short Chain Distribution of the Main Sleep Transistor ... 243
Power-off Latency Reduction ....................................................... 244
Programmable Main Chain Turn-on Control................................ 244
Sleep Transistor Design Metrics ................................................................ 250
Switch Efficiency .......................................................................... 250
Area Efficiency .............................................................................. 253
IR Drop.......................................................................................... 253
Normal vs. Reverse Body Bias ..................................................... 254

A.1.5 Recommendations ........................................................................ 259
A.2
A.2.1 Recommendations ........................................................................ 262
A.3
A.3.1 Recommendations ........................................................................ 263
A.4
APPENDIX B UPF Command Syntax........................................267
B.1 add_pst_state ............................................................................................ 268
B.2 connect_supply_net .................................................................................. 269
B.3 create_power_domain ............................................................................... 271
B.4 create_power_switch ................................................................................ 273
B.5 create_pst .................................................................................................. 275
B.6 create_supply_net ..................................................................................... 276
B.7 create_supply_port ................................................................................... 277
B.8 set_domain_supply_net ............................................................................ 278
B.9 set_isolation .............................................................................................. 279
B.10 set_isolation_control ................................................................................. 281
B.11 set_level_shifter ........................................................................................ 283
B.12 set_retention ............................................................................................. 285
B.13 set_retention_control ................................................................................ 287
B.14 set_scope ................................................................................................... 288
Glossary ......................................................................................291
Bibliography ...............................................................................293
Index ...........................................................................................297

dannymu

谢谢

bysg312

学习一下

gouyaer123

thank you very much well nice