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我编了一个简单的储存器程序,只能进行功能仿真,为何不能进行以后的仿真?
entity rom_1 is
Port ( wr , rd , cs : in std_logic;
ad : in std_logic_vector ( 7 downto 0 );
data_in : in std_logic_vector ( 7 downto 0 );
dout : out std_logic_vector(7 downto 0)
);
end rom_1;
architecture Behavioral of rom_1 is
subtype word is std_logic_vector(7 downto 0);
type memory is array ( 0 to 255 ) of word ;
signal adr : integer ;
signal sram :memory;
begin
adr <= conv_integer( ad ) ;
process ( wr , rd )
begin
if wr'event and wr ='1' then
if cs='1' and wr='1' then
sram ( adr ) <= data_in ;
end if ;
end if ;
end process;
process ( rd , cs )
begin
if( rd ='0' and cs ='1' ) then
dout<= sram ( adr ) ;
end if;
end process;
end Behavioral ;
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