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Modeling and simulation of cyclic digital-to-analog converter using VHDL-AMS
A Thesis submitted to the Division of Graduate Studies and Research of the University of Cincinnati
in partial fulfillment of the requirements for the degree of Master of Science
in the Department of Electrical and Computer Engineering and Computer Science
of The College of Engineering by
Gayathri Vaidyanathan
B.E., Birla Institute of Technology and Science, Pilani, India, 2003
This work and its defense approved by:
Chair:
Dr. Harold W. Carter
Dr. Carla Purdy
Dr. Wen-Ben Jone
Modeling and Simulation of Hierarchically Decomposed R-2R
Ladder DAC using VHDL-AMS
A Thesis submitted to the
Division of Graduate Studies and Research of
the University of Cincinnati
In partial fulfillment of the
requirements for the degree of
Master of Science
in the Department of
Electrical and Computer Engineering and Computer Science
of The College of Engineering
June, 2005
by
Lakshmi Chaitanya Durgaraju
B.Tech, (Electronics & Communication Engineering)
National Institute of Technology (REC), Warangal, India, 2002.
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