ADC 仿真，输入信号不给full-scale信号，而是-0.5dB full-scale是什么理由？

transistor7

请教一下，如题。多谢
很早之前看到过相关的解释，可现在找不到了。只是记得这样一个操作。

amswu

因为实际应用时考虑peak to average

transistor7

For avoiding the situation of overdriving the quantizer, the input signal is set to be -0.5dBFS or -1dBFS. Whether it is 1 dB or 0.5 dB below full scale, it is done so as to prevent clipping of the signal if one were to run the ADC inputs at full-scale (0 dBFS)
As we know 0dBFS input amplitude is equal to full scale.
-0.5dBFS is about 94.4 % of full scale.
-1dBFS is about 89.1% of full scale.