VCS syntax error

xiaoyisimonguo

in my design folder I have these verilog files:bandrate_generate.v  
ceshi_uart_test.v  
ceshi_uart.v  
uart_rx.v  
uart_tx.v

I used this command line to compile the test case:
vcs ceshi_uart.v bandrate_generate.v uart_rx.v uart_tx.v ceshi_uart_test.v -y . +libext.+v

and got error message:
Error-[SE] Syntax error
  Following verilog source has syntax error :
  "bandrate_generate.v", 5: token is 'module'
  module bandrate_generate ( input clk, input rst_n, input [1:0] state, output
  band_tick);
        ^
bandrate_generate
/*
* file name: bandrate_generate.v
* module bandrate_generate #(parameter bandrate = 9600) (
*/
module bandrate_generate ( input clk, input rst_n, input [1:0] state, output band_tick);
//此处initial语句是可以综合的，因为是预先计算的。
/************* initial the bandrate *******************/

2 warnings
1 error
CPU time: 1.168 seconds to compile


and the bandrate_generate.v read like this:
line 5:
module bandrate_generate ( input clk, input rst_n, input [1:0] state, output band_tick);

#------------------------------------------------#
I don't understand what did it complain. I failed to see anything wrong with the line 5

Please help

gaurson

bandrate_generate的完整代码能否贴一下？可以发图片。

liyaamd

回复 1# xiaoyisimonguo


   有没有加endmodule?

haoyz

endmodule加了吗？另外vcs是否添加了支持verilog2005命令？

tanju

遇到了这个问题，有个看法是，不一定实在module的地方有语法错误。可能是编译这文件之前的错误。