SUNG异步fifo style2 求解释

dyytx

The aempty_n signal might also stay high longer and go low at any moment, even perhaps coincident with the
next read clock edge. If it goes low well before the set-up time of the first synchronize flip-flop, the result is like
scenario (4) above. If it goes low well after the set-up time, the synchronizer will stretch rempty by one more read
clock period.

不知道有没有人看过这篇文章，这一段是在最后问题回答那一段，这里的说法是aempty_n会在任何时刻拉低，空应该是由读引起的，更读时钟同步，为什么会在任何时刻拉低？

constatine

nice，收藏了，很好