Cadence BJ 招聘资深数字前端验证工程师

kengteng

Cadence BJ 招聘资深数字前端验证工程师

更多职位信息敬请关注Cadence公众微信平台：Cadence_Recruitment

If you have interest, PLS send your update CV to zhangyl@cadence.com

Title: Principal/LeadVerification Engineer

Position Description:

Deliver/implementIP design. The engineer should be able to act as a strong team member andcontributor.

Specificduties include:

-Proficiency in logic design, simulation, synthesis, STA and testing

-Proficiency in Verilog and its simulation environment

At leastfive years experience driving complex IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment is required.

Position Requirements:         

BS degree with 6~10+ years of applicableexperience, MS degree with 4~7+ years of applicable experience in electricalengineering, microelectronics, comparable engineering science or solid statephysics. Essential that the individual demonstrates strong communication, verbaland written. Requires good communication skills in English.