【猎头】【新加坡】Senior Verification Engineer，3年以上

果汁控

大家好，我是新加坡Uni Connect公司（www.uniconnect.com.sg）的猎头周倩倩。我们公司在新加坡半导体行业做技术招聘已有15年经验，和各大公司合作密切。以下职位是一家提供多媒体和通信解决方案的大公司，工作地点在新加坡：

Senior Verification Engineer

Job Description
1. Constrained-Random Verification using SystemVerilog
2. Develop verification environment for DUT
3. Write and debug tests for DUT using SystemVerilog, Perl, and C.
4. Develop Bus Functional Model(BFM) or using Verification IP(VIP) for tests.
5. Developing and reviewing test plans
6. Write coverage monitors to evaluate the coverage of the DUT.
7. Formal verification using SystemVerilog Assertion to verify SOC or IP is plus

Job Requirement
1. >4+ ethernet switch background
2. At least 3-year+ experience on digital design and verification
3. Experience on SystemVerilog/VMM/OVM/UVM (UVM is plus)
4. Familiarity with transaction-level verification at higher-level of abstractions is plus.
5. Experiences in developing measurable verification plan.
6. Proficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl.



请发送您的英文简历到qianqian@uniconnect.com.sg。您还可以加我QQ：342403065，Skype：zhou.qianqian.uc，了解详情。


我的天际网页面：http://www.tianji.com/profile/zhouqianqian36