【全职招聘】AMD 上海热招各职位工程师、管理人员！

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1、Sr.ASIC Design Engineer  -           Display

DESCRIPTION OF DUTIES INADDITION TO THOSE IN JOB DESCRIPTION:

- Responsible for displayIP development and maintenance

- Responsible for IP levelsynthesis/CDC/LEC/LINT check

- Work with verification engineeron IP verification

- Work with front-endintegration team and physical design team on timing closure

- Communication withdriver team to build driver

PREFERRED EXPERIENCE:

- Bachelor with 5+ yeasand Master with 3+ in Electrical or Computer Engineering.

- Strong RTL coding andfamiliar with front-end design flow

- Experience on synthesis,timing analysis and formal verification.

- Experience of display specific-interconnection protocols(DisplayPort, LVDS, VGA,HDCP, DVI, HDMI etc) is a plus.

- Design for verification(assertion based design strategies, code coverage, functional

coverage, test plan etc.)

- Good communicationskills and fluent English.

- Strong responsibilitiesand team spirit.

2、D3Dengineer

DESCRIPTION OF DUTIES IN ADDITIONTO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.

PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or ElectronicEngineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.

3、DesignVerification MTS for Graphics Hardware

Job Description

Position  Title		Design Verification  MTS for Graphics Hardware
Organization	SRDC,  GC		Function	R&D
Location	Shanghai		Rep/Add	Add.

Position Summary

In thiskey role, the candidate will be responsible for low power implementation andverification of hardware.

Key Relationships

Report To:                    Manager ofSRDC

Direct Reports:              0

Essential Functions:

• Development of     infrastructure for verification of hardware in GFX IP.
• Develop     verification environments for feature verification, and use the automated     regression infrastructure setup for IP level and IP on SoC level     functional verification.
• Low power design     and verification for specific hardware functionality in Front-end.
• Improve the low     power IP delivery for variant SoCs

Requirements/Qualifications:

• BS, MS or PhD in     Electrical Engineering or Computer Science.
• 6+ years of ASIC     verification or low power design experience
• Should have good     understanding of Pre-Silicon design process from Architecture, Design,     Synthesis and Gate level Implementation till Tapeout release.
• Advanced     programming knowledge on Verilog/SystemVerilog, C/C++
• Requires     demonstrated technical expertise in the areas of Design Verification and     low power design/verification methodology.
• Knowledge on     Perforce, OVL, SVA, SV, UVM, script programming etc.
• Should have     excellent communication skills (both written and oral) and should be able     to participate cross functional engineering teams geographically.
• Demonstrates     leadership ability preferred.

Skills/Competencies:

·
Good design verification experience

·
Good communication

·
Strong problem solving skills

·
Low power design verification or computergraphics knowledge are plus

Desired:

·
Team Lead experience

·
Design Verification experience

4、Memberof technical staff for IC design engineering (MTS DE)

Requirements:

Thecandidate is preferred to be MSEE withminimum of 6 years, or BSEE with
minimum of 8 years experience in digital ASIC/SOC designengineering.  

It is a must that the candidate has one or more of thefollowing experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB)bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clockgeneration and control, SD/eMMC host controller, SATA/SAS, Legacy IPs(SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet,JTAG, etc.

Thecandidate is expected to exhibit good verbal and written communication skillsin both Chinese and English, specialized knowledge plus broad technicalknowledge that facilitates integrative thinking, , driving execution of qualityand timely result, capability  to solvecomplex, novel and no-recurring problems and decision-making on criticaltechnical areas

Responsibility:

Thesuccessful candidate will work with team members and apply his/her designtechniques to work on different phases of complex logic design for ASIC/SOCproject. The role will include technical leading on the following tasks fromtime to time: specification, top level SOC design tasks, HDL coding, etc.

5、Memberof technical staff for IC design verification (MTS DV)

Requirements:

The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience indigital ASIC/SOC design verification.

The candidate must have:

1.
deep understanding on ASIC/SOC design flow

2.
Excellent knowledge of design verification methodology, such asVMM or OVM and UVM.

3.
Solid experiences with simulation model creation and the testbenchbuild

4.
Strong RTLcoding with Verilog

5.
StrongSystemVerilog experiences.

6.
StrongC/C++ software development experiences

7.
Be good at scripting language, such as Perl, Cshell, Ruby,and  Makefile.

It is amust that the candidate has one or more of thefollowing experience/knowledge, such as X86/ARM/8051 architecture,AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NANDFlash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCIbus, low power design, clock generation and control, SD/eMMC host controller,SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), Ethernet, JTAG, etc.

The candidate is expected to exhibit goodverbal and written communication skills in both Chinese and English,specialized knowledge plus broad technical knowledge that facilitatesintegrative thinking, , driving execution of quality and timely result,capability  to solve complex, novel andno-recurring problems and decision-making on critical technical areas

Hands-on lab experience is another plus, ableto understand and/or use the use scopes, logic analyzers, has knowledge orskill of board-level lab debugging.

Responsibility:

The successful candidate will work with teammembers and apply current functional verification techniques to perform andimprove pre-silicon verification quality and product Time to Market forSouthbridge design. The candidate will provide the technical leadership to theDV team for the new Southbridge project. He/She should be able to workindependently on various DV tasks and providing technical guidance to the DVteam. The candidate would involve technically in the porting/creation of the DVenvironment for the new design, block and chip level test plan creation andimplementation, coverage analysis, and regression cleanup.

6、GFXDesign Verification

Job Description:

·
Work on the functional verification for the mostleading GPU chips in the industry: discuss with architects about thearchitecture, understand GPU design and verify the functional correctness forgraphics features on block level, sub-system level or SoC level.

Requirements

1.
More than 4-year work experience of verificationon block level or SoC level (2 years for Sr. Eng)

2.
Good knowledge of GraphicsPipeline/Algorithm/Application or Memory management is a must.

3.
Proficient in C++ programming is a must

4.
Familiar with at least one of the followinglanguage :  Verilog, System Verilog, OVM,  UVM

5.
Willing to take challenges and learn new things,have passion about the GPU design and algorithm

6.
Good at both Oral and written English

7.
Good at communication and team work skills

Or:

2.
Expert in C++ programming

3.
8 year+ work experience in SW programming in C++

4.
Good experience in working with NA team

7、StaffDesign Verification Engineer for Next Generation Interconnect IP

Job Title: Staff DesignVerification Engineer for Next Generation Interconnect IP
City/Town: Shanghai
Country: China

Job Description:
We are currently looking for Staff Engineers who will be responsible for allaspects of verification on next generation integrated interconnection fabricincluding IO Virtualization, PCIe, Hypertransport that is deployed in CPU &GPU. The verification work includes developing testbenches, modeling,assertions/checkers/monitors, test plan & test development, regressions,and infrastructure development. Responsibility includes participating in thepre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning,Implementation and Execution.
- Develop System Verilog (OVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for itsfunctionality and interface protocols and tracking bug reports. Creation of theneeded test libraries, test API, simulation models. Debugging regressionfailures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled environment,across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.

Requirement:
- 5+ years experience with Master degree or 7+ years experience with Bachelordegree.
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC orProcessor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR,DisplayPort) or multimedia/video is preferred.
- Good knowledge of SystemVerilog and OVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- Strong C and C++ software development and scripting languages (Perl, C Shell,Makefile, …) experience.
- Solid background with hardware verification methodologies such ascoverage-based verification methodology with the use of hardware assertions(PSL or SVA).

8、SeniorSoftware Development Engineer

Job Title: Senior Software Development Engineer

Windows Graphic Base Driver

ROLE & RESPOSIBILITIES

-
Work as part ofthe global base graphics engineering team to design and maintain the graphicsdevice driver

-
Resolve problem reports related to graphics device driver includingtroubleshooting, debugging, & defect correction

-
Specify, design, and implement new ASIC and software features

-
Coordinate closely with peers at both Asia and North America toensure timely and effective communication of all assigned work activities.

-
20%~50% traveltime between China Mainland and Taiwan expected.

DESIRED EXPERIENCE:

-
Experience inmulti-threaded programming in a x86 architecture in both kernel & usermodes.

-
Object-oriented design & programming

-
C/C++ programming

-
Experience with software debugging and related tool such as WinDbgor gdb in an x86 architecture in both kernel & user modes is a plus

-
Min. 3 years direct experience in Windows or Linux graphics driverdevelopment is preferred

-
Experience in Low-level programming of hardware devices ispreferred

-
Experience withdisplay technologies (DisplayPort, HDMI, Stereo 3D display, wireless display,etc.) is a plus

DESIRED KNOWLEDGE, SKILLS &CHARACTERISTICS

-
In depthunderstanding of PC architecture

-
In depth understanding of Operating System architecture

-
Good software debugging logic and hands on knowledge

-
Good verbal and written communication skill

-
Excellent multi-tasking and prioritization skill

-
Good team works

-
Self motivated,strong initiative, can work under moderate to minimal supervision

EDUCATION

-
BA/BS degree with strong academic background or equivalentexperience (higher level degree a plus) in Computer Science, ElectricalEngineering, Software Engineering. MS or PHD is a plus.

9、Principle/Senior Staff Design Architectfor 10GE+ IP

Position Summary

Job  Title:	Principle/Senior Staff Design Architect for 10GE+ IP
City/Town:	Shanghai
Country:	China

- Own IP architecturedefinition, derive functional and design specifications and analyze feasibilityof technical and architectures.

- Discuss with SWarchitect to generate an optimized HW/SW partition of the system architecture

- Guide the design teamto implement design with Verilog to achieve specification goals. Simulate anddebug the codes in coding stage.

- Support the Front-EndIntegration team to deliver qualified netlist. Feedback to Physical Design teamto help to close timing and check floorplan.

- Support FW/SW bring-upand debugging

- Working as the overalltechnical expert of contact on the 10GE area.   

Essential Functions:

Architecture, Algorithm, RTL,Performance modeling

EssentialRequirements:

-Rich Experience in 10GE+ IP solution, including HW IP and SW stack

- Deepunderstanding of

·
10GbE+ solutions from the industry leadingcompanies

·
basic offload engines used in 10GbE/40GbE,such as

o
TCPtransmit segmentation offloading

o
TCP Largereceive offload

o
Receiveside scaling

·
Basic filtering and Classification:Unicast/multicast/broadcast, ACLs

·
Advanced filtering and classification: flowbased and L3 protocol based

·
Data-center bridging, PFC/ETS/DCBX/QCN

·
Device virtualization, SR-IOV/VEB/VEPA

·
Advanced offload engine

o
TCPoffload: TOE

o
Storageoffload: iSCSI HBA/FCoE HBA

o
RDMA:RoCE/iWARP

o
Securityoffload: IPSec

·
PHY interfaces

- GoodEnglish hearing, speaking, reading and writing capabilities

- Goodcommunication skills

- Havemass production tape‐out experience

- Shouldhave strong problem solving skills

Position Summary

Job  Title:	Senior Staff/Staff Design Lead for Wired Connection  IP
City/Town:	Shanghai
Country:	China

- Participate IP and SoClevel architecture definition, create IP architectural spec, derive functionaland design specifications and analyze feasibility of technical andarchitectures.

- Implement design withVerilog to achieve specification goals. Simulate and debug the codes in codingstage.

- Define timingconstraints and support the FE Integration team to deliver qualified netlist.Feedback to Physical Design team to help to close timing and check floorplan

- Discuss with SW team togenerate an optimized HW/SW partition of the functionalities

- Support FW/SW bring-upand debugging

- Working as thetechnical point of contact in the Wired Connection IP area.

- Maintain designenvironment, solve flow issues, and develop scripts to improve flow efficiency.

                                                        

Essential Functions:

Architecture, RTL, Synthesis, STA, Timing Analysis, Constraints

Essential Requirements/Qualifications:

- Proven IP / SoC Design / Integration Experience

- Must have strong background on IP development

Desired:

- Enthusiasm on technical topics

- Major in EE & CS

- Must be proficient in Verilog coding, debugging and modeling

- Deep understanding of below technical aspects wouldbe an asset:

·
10GbE+ solutionsfrom the industry leading companies

·
basic offloadengines used in 10GbE/40GbE, such as

o
TCP transmitsegmentation offloading

o
TCP Large receiveoffload

o
Receive sidescaling

·
Basic filteringand Classification: Unicast/multicast/broadcast, ACLs

·
Advancedfiltering and classification: flow based and L3 protocol based

·
Data-centerbridging, PFC/ETS/DCBX/QCN

·
Devicevirtualization, SR-IOV/VEB/VEPA

·
Advanced offloadengine

o
TCP offload: TOE

o
Storage offload:iSCSI HBA/FCoE HBA

o
RDMA: RoCE/iWARP

o
Security offload:IPSec

- 10 gigabit+ Ethernet IP design experience would be an asset

- Ethernet HW/SW performance analysis experience wouldbe an asset

- Be familiarwith ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc

- Be familiar with shell/perl/tcl programming in linux OS.

- Should have strong problem solving skills

- Good English hearing, speaking, reading and writing capabilities

- Goodcommunication skills

- Have mass production tape‐out experience

10、Staff DesignVerification Engineer for Next Generation Interconnect IP

Job  Title:	Staff Design Verification Engineer for Next Generation  Interconnect IP
City/Town:	Shanghai
Country:	China
Job  Description:	Responsibility:    We are currently looking for Staff  Engineers who will be responsible for all  aspects of verification on next generation integrated interconnection fabric  including IO Virtualization, PCIe, Hypertransport that is deployed in CPU  & GPU. The verification work includes developing testbenches, modeling,  assertions/checkers/monitors, test plan & test development, regressions,  and infrastructure development. Responsibility includes participating in the  pre-silicon blocks, chip, multi-chip and system level verification strategy:    - Verification of SoC level  design using random methodologies – Test Planning, Implementation and  Execution.    - Develop System Verilog  (OVM) random sequences and methods.    - Maintain and Interface with  existing random generators, models and APIs    - Integration of random  modules to various testbenches.    - Executing verification  through directed and random tests for its functionality and interface  protocols and tracking bug reports. Creation of the needed test libraries,  test API, simulation models. Debugging regression failures and identify the  cause.    - Strong documentation and  communication skills.    - Ability to work well in a  dynamic, fast-paced, pressure filled, across multiple sites North America and  Asia    - Flexible in terms of  responsibilities and hours.       Requirement:    - 5+ years experience with  Master degree or 7+ years experience with Bachelor degree.    - Complex IP/ASIC/SOC Design Verification, direct experience in  IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB,  DDR, DisplayPort) or multimedia/video is preferred.    - Good knowledge of SystemVerilog and OVM is a plus.    - Good knowledge  of Verilog/C/C++/System C/SystemVerilog.    - Verification insights into  random techniques.    - Verification of large scale  ASICs.    - Experience in power  verification is an asset.    - Verification of  Virtualization Components is an asset.    - Strong C and C++ software  development and scripting languages (Perl, C Shell, Makefile, …) experience.    - Solid background with  hardware verification methodologies such as coverage-based verification  methodology with the use of hardware assertions (PSL or SVA).      11、Staff  Design/Integration Engineer for  Next Generation Interconnect IP         Position Summary           Job    Title:         Staff Design/Integration Engineer for Next Generation    Interconnect IP         City/Town:            Shanghai         Country:            China              -  Participate IP and SoC level architecture definition, derive functional and  design specifications and analyze feasibility of technical and architectures.       - Implement  design with Verilog to achieve specification goals. Simulate and debug the  codes in coding stage.       - Go  through the FE design flow to deliver qualified netlist. Feedback to Physical  Design team to help to close timing and check floorplan.       - Support  FW/SW bring-up and debugging       - Working  as the technical point of contact on the ASIC area.       - Maintain  design environment, solve flow issues, and develop scripts to improve flow  efficiency.                                                                   Essential  Functions:       RTL, Synthesis, STA, Timing Analysis, Constraints       Essential Requirements/Qualifications:          - Proven ASIC / SoC Design / Integration Experience      - Must have strong background on IP development             Desired:       - Major in EE & CS         - Must be proficient in Verilog coding, debugging and modeling      - Should be familiar with Advanced C++/SystemVerilog, RTL coding techniques.       - PCIe, Cache Management, MC, USB, BIOS, ACPI  experience would be an asset.    - Must be  familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO  etc      - Must be familiar with shell/perl/tcl programming in linux OS.      - Should have strong problem solving skills      - Good English hearing, speaking, reading and writing capabilities    - Good  communication skills      - Have mass production tape‐out experience      12、Software Engineering          Area of    Interest:         Software Engineering         Job Title:         MTS/SMTS Android Device Driver Development         Location         Shanghai         Country:         China         Job    Description:             DESCRIPTION OF    DUTIES:     - Provide    technical leadership in the development of device driver     - Closely    interact with ASIC design team in new feature definition and bring up for    future product generation     - Architect,    design and implement Android bus/device drivers and HALs for AMD ASICs     - Improve    customer satisfaction and product quality by fixing problems     - Accountable on    time delivery of deliverables     - Collaborate and interface with local and global    management, development and test teams to deliver a complete product    solution     - Regular communication via Audio/Video    conference with teams in North America             PREFERRED    EXPERIENCE:     - BS-CS/BS-EE    with at least 7 years experience in Android/Linux device driver    development, or 5 years experience for master degree     - Excellent and    demonstrable C/C++ programming skills     - Experience    with programming in C/Java interface would be an asset     - Experience    with Linux kernel mode driver programming under Android/Linux environment.     - Experience    with USB, SD, network, camera/ISP, A/V stream, power management, etc.    driver development preferred     - Experience    with PCI/PCI-E/AMBA/MIPI/I2C device driver development required     - Good    understanding of embedded system and/or tablet architecture is a plus     - Strong analysis and problem solving skills    required     - Proven    interpersonal skill, technical leadership and teamwork required     - Must be fluent    in both written and spoken English     - Experience    working with multi-site teams preferred          13、Sr.  Fro-end ASIC Design CAD engineer

Job Description

Position Title      Sr.Fro-end ASIC Design CAD engineer

Organization      Technologyand Engineering       Function              CAD

Location               Shanghai              Rep/Add              Rep

                                                                                

                                                                                

                                                                                

Position Summary

           Participatein the design and implementation of the leading edge, front-end ASIC designflow

           Participatein the research of Design Methodology to improve automation and  productivity to produce AMD's newhigh-quality cutting-edge APU and GPU products

           Technicalsupport and programming

           Interfacewith EDA vendors on technology

Key Relationships

Reports To: Angela Xue

Direct Reports: Angela Xue

               

Peer Relationships:         

Other Relationships:      

               

Essential Functions:

Essential Requirements/Qualifications:

1.            Majorin EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ yearsworking experience

2.            Experiencein Front-end digital design and VerilogHDL is required

3.            Goodprogramming skill with one or more languages (e.g. Tcl, Perl, python, c/c++,etc.) in Unix/Linux and a strong desire to automate flow

4.            Familiarwith SRAM design and behaviour is a plus

5.            Familiarwith one or more ASIC flows (logic synthesis, STA etc.) and usage of relatedEDA tools is a plus

6.            Goodwritten and spoken English

7.            Goodcommunication skills and be able to work both independently and in a team

14、LinuxGraphics 2d driver

DESCRIPTION OF DUTIES IN ADDITIONTO THOSE IN JOB DESCRIPTION:
- Design, code, optimize and maintain AMD Linux graphics display driver
- AMD new graphics ASIC bring up under Linux

PREFERRED EXPERIENCE:
- Mater degree or above in C.S. or E.E.
- Good knowledge of C/C++ programming
- Good knowledge of Linux kernel programming
- Good knowledge of graphics is a plus
- Good written and verbal communication skills
- 3+ years experience in C/C++ programming
- 3+ years experience in Linux kernel development and debugging
- 3+ years experience in Linux device driver development and debugging
- Experience in graphics driver development is a plus
- Experience in XServer/X.Org development is a plus
- Fluent English language communication skills (includingverbal/writing/reading), and CET-6 pass is a minimum

15、MTS/SEfor Camera/ISP SW Development (Android)

JD: MTS/SE for Camera/ISP SW Development(Android)

PREFERRED EXPERIENCE:

- BS-CS/BS-EE with at least 7 years’ experience in Android/Linuxdevice driver development, or 5+ years’ experience for MS

- Good at ARM assembly and C/C++ language,  demonstrableC/C++ programming skills

- Experience with Android camera HAL, camera service programming.

- Experience with Android multimedia OpenMAX frameworkintegration.

- Experience with Android kernel V4L2, camera sensor, VCM andflash driver programming.

- Experience with ISP, camera sensor tuning activity.

- Good understanding of embedded system and/or tablet architectureis a plus

- Strong analysis and problem solving skills required

- Proven interpersonal skill, technical leadership and teamworkrequired

- Fluent in both written and spoken English
- Experience of working with multi-site teams preferred

KEY Responsibilities:

- Architect, design and implement Linux/Android Camera/ISPsolutions for AMD Platform Solutions

- Closely interact with ASIC design team in new feature definitionand bring up for future product generation

- Improve customer satisfaction and product quality by solvingtechnical problems

- Accountable on time delivery of deliverables

- Collaborate and interface with local and global management,development and test teams to deliver a complete product solution

- Regular communication via Audio/Video conference with globalteams

15、 OpenGL MTS JD

DESCRIPTION OF DUTIES
- Implement OpenGL new features for new generation Graphic chips.
- Improve OpenGL benchmark performance.
- Work with key customers and vendors for implementation and issue solving.
- Interact with the Graphics Community .
Develop internal tools to improve development efficiency.

PREFERRED EXPERIENCE:
- Solid knowledge in C/C++ programming language, at least 5 years plus C/C++language experience.
- Solid knowledge in Computer Graphics.
- Strong knowledge in Linux kernal, 1 year plus Linux development experience
- Strong knowledge in software development life cycle.
- Strong knowledge in debug tools usage.
- High quality team player as good team working spirits and easy going withteam members.
- Prefer MS or higher education in CS or EE or Mathematic.

16、                Sr. ASIC/ Layout DesignEngineer (Verification CAD)

Title:

               Sr. ASIC/ Layout Design Engineer (Verification CAD)

Key Job Functions:

-
Understand the ASICdesign/verification flow and help design/verification engineers to accomplishtargets.

-
Develop infrastructureand environment for SOC/IP level chip design verification.

-
Closely working withDesign/Architecture/Verification team to develop new verification flow.

Preferred Experience:

-
Major in EE, CS orrelated, Master Degree with 3+ years or Bachelor with 5+ years workingexperiences

-
Familiar with LinuxEnvironment (including command shell scripting)

-
Skillful at scriptlanguage like ruby, perl, or tcl

-
Be good at C/C++programming

-
Should be versatile inany one of the high level verification flow such as SV,VMM,VERA,OVM etc as wellas knowledge of industry standard tools for verification

-
Should have excellentcommunication skills (both written and oral)

-
Strong problem solvingskills

-
Good knowledge onverification methodology

17、Sr.Manager for Display

Job Location: Shanghai

PREFERRED EXPERIENCE:

-
Master or PhD in Electrical Engineering or Computer Science.

-
10+ years of relevant experiences in related industry

-
In management position with global company and leading a team with20+ engineers for 5+ years with Multi-site experience

-
Excellent English communication skills in both speaking andwritten.

-
Strong knowledge with C/C++, Verilog, Synthesis, Timing, PhysicalDesign process

-
Strong experience of display specific-interconnection protocols(DisplayPort, HDMI, LVDS, VGA, DVI, etc) or Display process

-
Plus on Graphic or real time display related knowledge

-
Team player with open mind