[招聘]Marvell急招后端工程师

Hwangbo

If youhave any interest in the position, please send your bilingual resume as

attachments to
al-china-hr@marvell.com
Subject of your email should be “YourName_University_Applied Position Title”

1\JobTitle: Physical Design Engineer

Department: COT PD-SH -MTSL

Location: Shanghai / Chengdu/Beijing

JobDescription:

Physical Design Engineer will supportphysical design requirement of different business unit of Mavell, the mainresponsibility is:

physical implementation, including floorplan,power routing, placement, clock tree synthesis, timing closure, routing, sifixing, drc fixing, dfm ...etc

physical verification: including low powercheck, timing analysis, timing eco, xtalk analysis, power analysis, ESDanalysis, EM analysis, drc check, lvs check, ant check, erc check ...etc

tapeout: timing signoff, power signoff,design tapeout... etc

Qualification:

BS/MS in EE/CS required.

Some knowledge and some experience onprocess, parameters, synthesis, timing analysis, placement, routing, CTS, SI,power calculation, custom layout, timing analysis and DRC/LVS.

Familiar with Cadence, Synopsys, Mentor,Magma, Apache… EDA tools and design flow;

Familiar with Verilog HDL, Spice

Good programming skill. Capable of writingTcl or Perl.

Self-motivated team worker, good verbal andwritten communication skills in English

2\Job Title:Engineer, Senior ASIC Design

Department: CentralEngineering
Location: Beijing/Shanghai/Nanjing

JobDescription:

Asa Digital design engineer, he/she will contribute to the overall SoCdevelopment and IP development for the micron-controller oriented SoC Productline, which includes block level micron-architecture design, RTL coding,Simulation, SoC top level integration, verification and chip bring-up.

Qualification:

BS degree inElectrical Engineering +5 years experience (or MS + 3 years) or equivalent inhardware development and system architecture.

Familiar with ASIC design methodologies and flows.

Experience in the usage of state-of-the-art design tools.

倠爀漀昀椀挀椀攀渀琀 in behavioral and RTL coding, Verification. Verilog is preferred
  Experience in logic synthesis, timingclosure.

Experience in Design For Test.

Knowledge of Low Power architecture and design practice is desirable.

匠琀爀漀渀最 verbal and written communication skills and proactive team-work spirit.

圠漀爀欀椀渀最 understanding of various system interconnect protocols such as: AHB,AXI, OCP, APB, and their impact on IP development.

QQ:1552937745

MSN: domiliu0801@hotmail.com  更多Marvell招聘职位，请访问
http://marvell.cnstaff.com/

Hwangbo

急招中，HC已审批！有兴趣的朋友欢迎投递简历. al-china-hr@marvell.com

jimmylaw

请问职位面向应届生吗？

chendiyi

回复 1# Hwangbo
你好，LZ,这职位面向应届生么？

惊波方休2

好单位。