[猎头职位]DIGITAL DESIGN ENGINEER/Backend Leader

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DIGITAL DESIGN ENGINEER 3G MULTIMEDIA & PLATFORM









Department    Analog Mixed Signal for 3G MULTIMEDIA & PLATFORMS (3GP)

The BU (Business Unit) Analog Mixed Signal within 3GP develops, produces and sells advanced, highly integrated CMOS system Portable Power Solutions for Multimedia & Platforms. Our main customers are Nokia, Samsung and Sony Ericsson. The BU has it’s headquarter in Grenoble and it’s design operations in Grenoble, Catania, Prague and Shanghai. Currently it employs about 300 persons.



Job Summary    As a Digital Design Engineer you are member of one or our PMU product development teams. You will be developing digital control circuits for innovative mixed signal high voltage (20 V) CMOS ICs. You fulfill an important role in the integration of these modules into PMUs (top-level design and simulations). The role will cover the full IC design cycle from specification through to testing of engineering samples.



Key Areas of Responsibility    1．Design & Development

o Translating requirements (IP, IC) into implementation specifications

o Development of digital IP (VHDL & Verilog coding, synthesis) and mixed signal IP (schematic level) taking into account all requirements

(power usage, functionality, timing, size)

o Together with test engineering making the designs industrial testable aiming for proper coverage and optimized test times (DFT)

o Taking care of configuration data management on IP and IC level and able to fulfill role as project integrator

o Integration of top level mixed signal power management IC’s

o Support project teams with debugging and finding solutions for products not performing to specification both on IP and IC level

2. Verification

o Responsible for verification and evaluation (i.e. Verification Plan and Verification Results).

o Analyses design flaws  
o Conducts corrective actions (processes PRs & CRs).

3. Quality of work

o Is responsible for quality of own design.

o Improves designs over time, by applying lessons learned.

o Ensures completeness of the (module) documentation.

o Is co-responsible for review of own work.

4. Schedule & Efficiency

o Defines a reliable schedule for own work in order to support project management.

o Reports progress of own activities.

o Makes optimally use of known and verified (sub)modules in order to reduce project risks and development effort.

o Contributes to balancing amount of work among peer developers.

5. Communication

o Communicates with clarity, structure and conciseness both verbally and in writing

6. Coaching

o Coaches less experienced colleagues when needed or asked for.



7. Learning & Development (Personal Development)

Maintaining capabilities, increasing added value, enhancing deployment.  
o Keeps abreast of current technology and deploys new methodologies

o Knows technology trends and deploys them

o Searches for new challenges to broaden or deepen expertise

o Improves areas of weakness (technical, behaviors, attitudes)



Requirements    BSEE/MSEE

5 years experience in digital design

- Experienced with mixed signal IC design;

- Able to build Verilog-AMS models;

- Able to run mixed-level simulations;

- Experienced with Synopsys & Cadence tool suite;

- A team-worker with a pro-active attitude; Open in communication   













Backend Leader





Job Description:

1. Lead a team: Build up high performance backend team, participate in the recruitment, setup the objectives, do performance review, support and coach team members

2. Do backend resource allocation, and mediates on short-term priorities

3. Can act as project backend work package leader, manage work package execution from definition to qualification within schedule and quality standard

4. Ensure the technical leadership

5. Coordinate backend team’s activity with other teams locally and worldwide

6. Support quality process in Shanghai site

Requirements:

-B.Sc. degree or above in Semiconductor, Electronics Engineering areas

-8 year or above experience in backend SoC design with proven SoC tapeout experience

-Have backend team/project management experience

-Strong expertise in Synthesis, floorplan, PnR, SI, LP design, CTS, power analysis in deep sub-macro design.

-Strong timing closing and power optimization capabilities.

-Strong experience in synopsys/cadence design tools and flows.

-Excellent analytical, debugging and solving skill

-Experience in data management tools such as DesignSync or Clearcase

-Experience in Frontend and DFT is plus

-Open mind, self-motivated, good communication skills

-Good communication skill, will have frequent communication with foreign teams.

-Good written and spoken English is mandatory







Grace Li

Principal Consultant & General Manager @ Hi-Talent Consulting Co. , Ltd.

上海芯相会企业管理咨询有限公司

E-Mail: bestgrace@qq.com

QQ: 2043753191

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