Cadence SH 招聘 Lead Verification Engineer

kengteng

Lead Verification Engineer

Position can be basedin: Shanghai/Beijing

Deliver/implement advancedverification solutions by utilizing Cadence’s Incisive Verification productportfolio. The engineer should be able to act as a strong team member andcontributor,leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

--Deep understanding on ASIC/SOC design flow

--Excellent knowledgeof advanced verification methodology like eRM/OVM/UVM

–Familiar withCadence’s Incisive Plan to Closure Methodology (IPCM)

--Proficiency in SystemVerilog, System C and/or e (Specman)

–Developing and usingVerification Components (eVC,OVC,UVC,VIP)
–Developing and using assertion based verification andformal analysis methods

--Skilled inscripting language,such as Perl,C shell,Python,Makefile
–Assessing the project verification requirements
–Operating in a lead role regarding architecting andimplementation of project verification environment/solution.

–May coordinate/leadothers within the scope of a defined project

EssentialQualifications: Must have BS degree with 5+years of applicable experience,MS degree with 4+years of applicable experience
inelectrical engineering,microelectronics,comparable engineering science or solidstate physics. Essential that the individual demonstrates strong communication,verbaland written. Requires good communication skills in English.

DesirableQualifications: Aminimum of four years relevant experience in industry.

- Will havedemonstrated hands-on experience and expertise with Cadence verification designtools or equivalent tools,flows and methodologies required to execute a verificationproject.

- Will have demonstratedsuccessful completion of 6+ verificationprojects as an individual contributor

- Will haveDDR project verification experience

If youhave interest, PLS send your update CV to zhangyl@cadence.com