请大虾们帮我看看下面的程序（Verilog），怎么仿真时老是出错啊？？

stonelet

源程序：
module mytak;
reg clock,red,amber,green;
parameter on=1,off=0,red_tics=350,
amber_tics=30,green_tics=200;
initial red=off;
initial amber=off;
initial green=off;
always
    begin
         red=on;
    light(red,red_tics);
    green=on;
    light(green,green_tics);
    amber=on;
    light(amber,amber_tics);
    end
  task light(color,tics);
      output color;
      input[31:0] tics;
     begin
   repeat(tics) @(posedge clock);
   color =off;
        end
   endtask
   always
      begin
    #100 clock=0;
    #100 clock=1;
      end
endmodule
仿真时的错误提示：
# ** Error: C:/Modeltech_5.8/examples/mysimulate1/mytak.v(18):
near "color": expecting: INOUT INPUT OUTPUT
# ** Error: C:/Modeltech_5.8/examples/mysimulate1/mytak.v(21):
ear "begin": syntax error
# ** Error: C:/Modeltech_5.8/examples/mysimulate1/mytak.v(22):
near "@": expecting: ';'
# ** Error: C:/Modeltech_5.8/examples/mysimulate1/mytak.v(23):
near "=":  expecting: IDENT