VHDL新手急：这种错误是什么原因造成的？

yunlong

我用的是ISE6.1软件，芯片选的是XC95144-7PQ160，用VHDL写的程序，综合通过，但是在FIT时出现错误，提示如下：
Started process "Fit".
Release 6.1i - CPLD Optimizer/Partitioner G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Considering device XC95144-7-PQ160.
Flattening design..
Multi-level logic optimization...
Timing optimization..............................................................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 133 equations into 8 function blocks...........................ERROR:Cpld:892 - Cannot place signal ADC_STCK_HH<1>. Consider reducing the
   collapsing input limit or the product term limit to prevent the fitter from
   creating high input and/or high product term functions.
See the fitter report for details.
..................................
字符转换错误：“Unconvertible UTF-8 character beginning with 0xbc”（行号可能太小）。
line number 1
Entity null
Failed to open: sample_build.xml
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason:
Process "Fit" did not complete.
对第一个错误，我修改过collapsing input limit和the product term limit，但是还是没能通过FIT；对于字符转换错误一直都有，不知是什么原因。
这些是由于对ISE6.1设置不对还是95144资源不够用造成的？我也换过大一些的芯片，如95216，但是还是出现相同的错误。
如果哪位愿意指点，我想请他看看源码。
很急，请大家指点，不胜感激！

bravelu

“See the fitter report for details.”
把你的fit report 贴出来看看？

beibeilong1

程序都没有,怎么看