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本帖最后由 dirk888 于 2012-5-27 02:56 编辑
成都大型IC设计公司招聘LAYOUT工程师，有兴趣请发简历到:ever_lin@163.com
职位介绍和要求如下：
Job Description:
Improve standard cell library layout architectures for tradeoffs in size, speed, density and yield for targeted applications. The designer should have a clear understanding of standard cell layout constraints and be able to drive trade-offs and new rule creation. The candidate will be working closely with circuit design to help optimize standard cells, and complete libraries, to take advantage of cutting edge layout dependent effects to improve the overall library performance.
Qualifications:
-BSEE with more than 2 years of experience or MSEE with 1 or more years of experience
-Cutting edge, 28nm and below technology node experience a plus.
-The candidate should be proficient with transistor level layout and related tools such as Cadence Virtuoso or Springsoft Laker, as well as Calibre DRC/LVS or equivalent tool set.
-They should have experience running the complete layout design flow including schematic to layout generation, DRC, LVS, ERC and DFM verification and validation.
-Experience in parasitic extraction a plus.
-Good team work spirit, easy to cooperate with team members |
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发表于 2012-5-23 20:26:00
