|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
本帖最后由 b12345tt 于 2012-4-10 22:12 编辑
在下之前发过这个问题的帖子了,之后又在edaboard上发了这个问题,可能是之前发的现象没描述清楚,下面把在下的问题再行描述
跪求各位大神解答,谢谢~
之前帖子的传送门:http://bbs.eetop.cn/thread-327909-1-1.html
In a layout, I put both NW and NWH over a 5V PMOS, as follows
Could anyone please tell me what it affects?THX
The circuit shown as follows, in the test, if the IN is high, the output is high, but if the IN is low, the output turns to high from low afer 58ms, and there are signs that a large current about 1mA produced between VDD and VSS, thus we suppose the overlap of NW and NWH change the function of the PMOS, but we don't know how it works
schematic
|
|