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英特尔西安研发中心急招数字IC验证工程师。机不可失,感兴趣的朋友千万不要错过与大牛们共事的机会哦。
工作地点:西安 联系人:郭小姐 电 话:0571/28829923 邮 箱:758459601@qq.com
Job Description: Interface to Hardware Architects (Concept Engineering) and Physical Implementation Team Assisting clock, reset and power concept definition together with Concept Engineering Defining design implementation specification (module or sub-system level) VHDL or Verilog Coding Internal and/or external IP integration Test-bench generation and test-case preparation according to verification plan Gate-level simulation Test pattern generation (interface to IC Test Development Engineer) and debug support Timing constraint definition/review (interface to Physical Implementation Team) STA timing analysis support (interface to Physical Implementation Team)
Requirements: 3+ years experience Familiar with mainstream simulators (Modelsim and/or Affirma) Scripting/programming languages (PERL and/or TCL and/or C, etc) Knowledge on Design Compiler Understanding of timing analysis and physical implementation
Understanding of DFT (Design for Test) concept Fluent in spoken and written English (CET6 is desired) |
英特尔西安研发中心急招数字IC验证工程师。机不可失,感兴趣的朋友千万不要错过与大牛们共事的机会哦。
工作地点:西安 联系人:郭小姐 电 话:0571/28829923 邮 箱:758459601@qq.com
Job Description: Interface to Hardware Architects (Concept Engineering) and Physical Implementation Team Assisting clock, reset and power concept definition together with Concept Engineering Defining design implementation specification (module or sub-system level) VHDL or Verilog Coding Internal and/or external IP integration Test-bench generation and test-case preparation according to verification plan Gate-level simulation Test pattern generation (interface to IC Test Development Engineer) and debug support Timing constraint definition/review (interface to Physical Implementation Team) STA timing analysis support (interface to Physical Implementation Team)
Requirements: 3+ years experience Familiar with mainstream simulators (Modelsim and/or Affirma) Scripting/programming languages (PERL and/or TCL and/or C, etc) Knowledge on Design Compiler Understanding of timing analysis and physical implementation
Understanding of DFT (Design for Test) concept Fluent in spoken and written English (CET6 is desired) |