AMD-BJ “ASIC Design Verification Engineer for SoC”

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AMD是一家专注于微处理器设计和生产的跨国公司，总部位于美国加州硅谷内森尼韦尔。AMD为电脑、通信及消费电子市场供应各种集成电路产品，其中包括中央处理器、图形处理器、闪存、芯片组以及其他半导体技术。
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Responsibility:
We are currently looking for  Senior Design Verification Engineers who will be responsible for all aspects of verification on next generation integrated processors (CPU + GPU + Multi Media) chipset, including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development.

Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
-        Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
-        Develop System Verilog (OVM) random sequences and methods.
-        Maintain and Interface with existing random generators, models and APIs
-        Integration of random modules to various testbenches.
-        Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
-        Strong documentation and communication skills.
-        Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
-        Flexible in terms of responsibilities and hours.


Requirement:
-        3+ years experience in complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (PCI-e, MC, HT) or multimedia/video is preferred.
-        Good knowledge of SystemVerilog and OVM is a big plus.
-        Good knowledge of  Verilog/C/C++/System C/SystemVerilog.
-        2+ years experience in Verification.
-        Verification insights into random techniques.
-        Verification of large scale ASICs.
-        Working knowledge of x86 assembly programming is an asset.
-        Experience in power verification is an asset.
-        Verification of Virtualization Components is an asset.
-        Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
-        Strong background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).