Silicon Modeling of Nanometer Systems-on-Chip

drjiachen

Abstract
Given that more than half of mixed signal designs are
failing first silicon, SoC designs require a comprehensive
approach to parasitic extraction that satisfies the needs for
accuracy, performance and detailed analysis. Parasitic
extraction tools need to provide not only comprehensive
evidence of unintentional parasitic effects, but also
accurate data for accurate analysis. These analysis
requirements may include: Static Timing (C or RC) for
traditional timing analysis and overall net delay; Dynamic
Timing (C or RCC) for propagation delay with all circuitry
active; Noise (RC) for crosstalk and signal integrity issues;
Power (R) for IR drop and hotspots; and, Reliability (R) for
yield analysis and electromigration. The design styles
found in SoCs, be they analog, memory, full custom, etc.,
require a comprehensive approach to extraction. Designers
need an LVS-parasitic extraction tool suite that provides
gate-level, transistor-level, and mixed-level analysis, plus
accuracy, capacity and performance across all design
styles to obtain accurate silicon modeling.

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Daniel10003

呵呵，谢谢楼主

yesowen

谢谢分享