Testing SoC interconnects for signal integrity using extended JTAG architecture

drjiachen

Abstract—As technology shrinks and working frequency reaches the
multigigahertz range,designing and testing interconnects are no longer
trivial issues. In this paper,we propose an enhanced boundary-scan architecture
to test high-speed interconnects for signal integrity. This architecture
includes: 1) a modified driving cell that generates patterns according
to multiple transitions fault model and 2) an observation cell that monitors
signal integrity violations. To fully comply with the conventional Joint Test
Action Group Standard,tw o new instructions are used to control cells and
scan activities in the integrity test mode.

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