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Key Features | - Metal programmable ROM 128kx8 in 0.35µm CMOS Process (C35/S35)
- Area optimized architecture
- Synchronous interface / access
- Two layer programmable (VIA1 & METAL1)
- Triple metal layout of memory
- 128k words
- 8 bit databus
- Simulation models for 3.3V nominal supply
| Deliverables | - Frontend services
- CADENCE
- cell library with symbol, functional, abstract and msps view
- TLF 3.0 & TLF 4.3 timing data file
- LEF file for silicon ensemble
- SDF annotable Verilog model
- SYNOPSYS
- cell timing model (interface model)
- Backend Services (on order)
- CADENCE
- cell library with additional layout view with reduced layout data (*)
- gds2 data
- reduced layout data in gds2 format (*)
(*) reduced layout data does not contain the following layers:
- Diffusion
- Poly1
- N+ Implant
- P+ Implant
- Contact
The reduced layout data will be replaced with full layout data by austriamicrosystems before production.
| Area | Area [mm2] | Process | 128k x 8 | C35 | 3.91 |
| Timing | Access Time [ns] | Process | 128k x 8 | C35 | 9.5 |
| Power consumption |
Supply Current [mA/MHz] | Process | 128k x 8 | C35 | 0.25 |
Power and Timing data conditions: | - typical process parameters
- VDD = 3.3V
- Tj = 25C
- Cload = 1pF
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| Description | This instance is a VIA1 & MET1 programmable ROM device. The 2 layer programming concept guarantees a high density ROM block.
Please note: The instance is not included in the standard HIT-Kit shipment. Memory Simulation models can be downloaded free of charge, reduced layout data including connectivity and metal coverage information is provided after placement of a purchase order whereas the complete layout data of the ROM block will be inserted into your design by austriamicrosystems' Customer Engineering once you have submitted the GDSII database for manufacturing. |
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