AMD 南桥部门内部推荐

chyzhj

现在我们部门急需招聘20多个Design/Verification Engineer,有合适的可以把简历发给我，如果觉得合适的话我会直接递交给我们老大，因为是部门内部推荐，所以成功的几率很大，欢迎优秀人士加入我们team. 谢谢
yong1.chen@amd.com

Job Title:
Staff ASIC/Layout Design Engineer__South Bridge
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION :
The AMD South Bridges Group has openings for a MTS/Sr. Design Verification
Engineer. The successful candidate will apply current functional verification techniques
to perform and improve pre-silicon verification quality and product Time to Market for
Southbridge design. He/She should be able to work independently on various DV tasks

and providing technical guidences to the DV team. The candidate would involve
technically in the porting/creation of the DV environment for the new design, block and
chip level testplan creation and implementation, coverage analysis, and regression
cleanup.
PREFERRED EXPERIENCE:
- MSEE,BSEE or equivalent degree,
- Minimum of 3 years of ASIC design verification experience.
- Knowledge of design verification methodologies.
- Some of the peripheral I/O interfaces, such as PCIE, USB, SATA,PCI, SD, JTAG or
Ethernet.
- Shell/perl/Makefile programming in linux OS.
- Verilog design/simulation and SystemC/C++ programming
- Hardware assertion languages such as PSL/SVA,
- Test bench creation and functional coverage with HDL's such as System Verilog or
SystemC.
- Good verbal and written communication skills in both Chinese and English.

Job Title:
Sr. DV Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION :
We are currently looking for an Senior Eng Design Verification Engineer who will be
responsible for all aspects of verification on next generation integrated processors chipset,
including developing DV infrastructure environment, testbenches, modeling,
assertions/checkers/monitors, test plan & test development, regressions, and
infrastructure development. Responsibility includes participating in the pre-silicon blocks,
chip, multi-chip and system level verification strategy:
- Verification of Graphic North Bridge design using complex DV environment C/C++,
SystemVeilog, OVM, SystemC, Verilog - Infrastructure development
- Experience in use of front end CAD tools Synopsys (VCS, )
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, multiple sites North
America and Asia
- Flexible in terms of responsibilities and hours.
PREFERRED EXPERIENCE:
- Bachelor/Master in Electrical/Computer Engineering.
- Strong C and C++ software development and scripting languages (Perl, C Shell,
Makefile, …) experience.
- Good knowledge of SystemVerilog and OVM is desirable.
- 3+ years experience in Verification in a large scale ASIC design environment.

- Strong background with hardware verification methodologies such as coverage-based
verification methodology with the use of hardware assertions (PSL or SVA).
- Strong analytical thinking skills, excellent attention to detail, and good coding skills
are required.
- Must be organized, enthusiastic self-starter and have good communication skills and
the ability and desire to work as a team.

o2real

你好，请问工作地点在哪里

chyzhj

上海浦东新区张江集垫港二期，广兰路地铁站旁边