编写PCI程序时,仿真的问题.

cqm239

module config_mux (pci_dat_out, ba0_size, ba1_size, bkend_dat,
                   pci_dat, pci_cbe_l, pci_addr, pci_rst_l,
                   abort_sig, pci_clk, com, cbe_reg_l,
                   idsel_reg, ba0, ba1, pci_irdy_l ,pci_ad);

  output [31:0] pci_dat_out; // the pci output data bus
  output [31:4] ba0_size; // The address space required for ba0
  output [31:4] ba1_size; // The address space required for ba1
  output [1:0] com; // The Mem - I/O enable bits of the command reg
  output [31:0] ba0;
  output [31:0] ba1;

  

  input pci_irdy_l;
  input [3:0] cbe_reg_l;
  input idsel_reg;
  input [31:0] bkend_dat; // back end data in
  input [7:0] pci_addr;
  input [31:0] pci_dat; // pci data
  input [3:0] pci_cbe_l; // byte enables in

  input pci_rst_l; // async reset
  input abort_sig; // state machine is aborting set status
  input pci_clk;  
  input [31:0] pci_ad;


reg [7:0] int_line; // r/w interupt line register
reg [31:0] pci_dat_out; // output data bus
reg [31:0] cfg_dat_out; // output data bus
reg [1:0] com; // The command register
reg stat11; // The status register bit for signaled target abort
reg stat_com_en;
reg int_line_en;
reg ba1_en;
reg ba0_en;


wire cfg_en;
reg cfg_out;
reg [31:0] ba0; // output data bus
reg [31:0] ba1;


parameter        DEVICE_ID     = 16'h0120; // User Defined
parameter        VENDOR_ID     = 16'h1022; // Set to AMD

`define fast    2'b00
`define medium  2'b01
`define slow    2'b10
parameter DEV_SEL = `slow; // medium devsel timing

always @ (posedge pci_clk or negedge pci_rst_l)
  if (pci_rst_l == 1'b0)
   begin
     com <= 2'b00; // disable I/O and MEM space accesses.
     stat11 <= 1'b0; // reset target abort status bit
  end
  else if (stat_com_en == 1'b1) begin
      if (!pci_cbe_l[0])  // check to see if byte lane is enabled
        com <= pci_dat[1:0];
      else
        com <= com;
      if (!pci_cbe_l[3] && pci_dat[27]) // check to see if byte lane is enabled
        stat11 <= 0;                  // write a 1 clears this bit
      else
        stat11 <= stat11;   
  end
  else if (abort_sig == 1'b1) begin
     stat11 <= 1'b1; // set target abort status bit
     com <= com;
  end
  else begin
    stat11 <= stat11;
    com <= com;
  end






parameter        CLASS_CODE    = 24'h058000;        // Memory Controller
parameter        REVISION_ID   =  8'h01;                // Rev. 01




parameter MISC_FUNCTIONS = 32'h00000000;


`define MEM_ON         1'b0
`define IO_ON          1'b1

`define ANYWHERE_IN_32 2'b00
`define BELOW_1M       2'b01
`define ANYWHERE_IN_64 2'b10

`define PREFETCH_ON    1'b1
`define PREFETCH_OFF   1'b0

`define ADDR_2G     28'h8000_000
`define ADDR_1G     28'hC000_000
`define ADDR_512M   28'hE000_000
`define ADDR_256M   28'hF000_000
`define ADDR_128M   28'hF800_000
`define ADDR_64M    28'hFC00_000
`define ADDR_32M    28'hFE00_000
`define ADDR_16M    28'hFF00_000
`define ADDR_8M     28'hFF80_000
`define ADDR_4M     28'hFFC0_000
`define ADDR_2M     28'hFFE0_000
`define ADDR_1M     28'hFFF0_000
`define ADDR_512K   28'hFFF8_000
`define ADDR_256K   28'hFFFC_000
`define ADDR_128K   28'hFFFE_000
`define ADDR_64K    28'hFFFF_000
`define ADDR_32K    28'hFFFF_800
`define ADDR_16K    28'hFFFF_C00
`define ADDR_8K     28'hFFFF_E00
`define ADDR_4K     28'hFFFF_F00
`define ADDR_2K     28'hFFFF_F80
`define ADDR_1K     28'hFFFF_FC0
`define ADDR_512    28'hFFFF_FE0
`define ADDR_256    28'hFFFF_FF0
`define ADDR_128    28'hFFFF_FF8
`define ADDR_64     28'hFFFF_FFC
`define ADDR_32     28'hFFFF_FFE
`define ADDR_16     28'hFFFF_FFF





parameter [31:0] BA0 = {`ADDR_16,`PREFETCH_OFF,`ANYWHERE_IN_32,`IO_ON};
assign ba0_size = BA0[31:4]; // Used to decode hit_ba0_l
/******************************************************************/
/************    End Reg 10h Section              *****************/
/******************************************************************/




// reg 14h (Base Address 1) BA1 Using `defines from above
parameter [31:0] BA1 = {`ADDR_2K,`PREFETCH_OFF,`ANYWHERE_IN_32,`MEM_ON};
assign ba1_size = BA1[31:4]; // Used to decode hit_ba1_l

always @ (posedge pci_clk or negedge pci_rst_l)
    begin
      if (pci_rst_l == 1'b0) begin
          ba0 <= BA0;
          ba1 <= BA1;
        end
      else if (ba0_en == 1'b1) begin
          ba0[31:4] <= pci_ad[31:4]&BA0[31:4]; // write the base address during a config cycle
      end
      else if (ba1_en == 1'b1) begin
          ba1[31:4] <= pci_ad[31:4]&BA1[31:4]; // write the base address during a config cycle
      end
      else begin
        ba0 <= ba0;
        ba1 <= ba1;
      end  
    end



// reg 2Ch (SubsystemID/Subsystem VendorID)
parameter        SUB_SYSTEM_ID = 16'h0120; // User Defined Could be anything
parameter        SUB_VENDOR_ID = 16'h1022; // Set to AMD





// reg 3C (Max_Lat/Min_Gnt/Interrupt Pin/ Interupt Line)
// Interupt Pin is set to 1 corresponding to inta_l

parameter INT_PIN = 8'h01;

// The int_line reg is defined here
// The software will write to this register
// to set the system IRQ used for the interrupt
always @ (posedge pci_clk or negedge pci_rst_l)
  if (pci_rst_l == 1'b0) begin
    int_line = 8'h00;
  end
  else if (int_line_en && !pci_cbe_l[0] ) begin // check byte enables
    int_line = pci_dat[7:0];
  end
  else begin
    int_line = int_line;   
  end
`define write_04 (pci_addr[7:0] == 8'h04)
`define write_10 (pci_addr[7:0] == 8'h10)
`define write_14 (pci_addr[7:0] == 8'h14)
`define write_3C (pci_addr[7:0] == 8'h3C)

assign cfg_en = (cbe_reg_l == 4'b1011 && idsel_reg == 1'b1) ? 1'b1 : 1'b0;

always @ (cfg_en or pci_irdy_l or pci_addr[7:0])
begin
  if (cfg_en && !pci_irdy_l) begin
    if (`write_04) begin
      stat_com_en <= #1 1;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
      end
    else if (`write_10) begin
      ba0_en <= #1 1;
      stat_com_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
      end
    else if (`write_14) begin
      ba1_en <= #1 1;
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      int_line_en <= #1 0;
      end
    else if (`write_3C) begin
      int_line_en <= #1 1;
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      end
    else begin
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
    end
  end
  else begin
      stat_com_en <= #1 0;
      ba0_en <= #1 0;
      ba1_en <= #1 0;
      int_line_en <= #1 0;
  end
end





always @ (posedge pci_clk or negedge pci_rst_l)
  begin
    if (!pci_rst_l) begin
        cfg_out <= #1 1'b0;
      end
      else if (cbe_reg_l == 4'b1010) begin
        cfg_out <= #1 1'b1;
      end
      else begin
        cfg_out <= #1 1'b0;
      end
  end

always @ (cfg_dat_out or bkend_dat or cfg_out)
begin
  if (cfg_out) begin
      pci_dat_out <= #1 cfg_dat_out;
    end
  else
    begin
      pci_dat_out <= #1 bkend_dat[31:0];   
    end
end




always @ (posedge pci_clk or negedge pci_rst_l)
begin
  if (!pci_rst_l) begin
        cfg_dat_out <= #1 32'b0; // zero at reset
      end
      else begin
        case (pci_addr [5:2])
          4'b00_00: cfg_dat_out <= #1 {DEVICE_ID,VENDOR_ID};// reg 00h (DevID/VendorID)
          4'b00_01: cfg_dat_out <= #1 {4'b0,stat11,DEV_SEL,9'b0,14'b0,com};//reg 04h (status/command)
          4'b00_10: cfg_dat_out <= #1 {CLASS_CODE,REVISION_ID}; // reg 08h (Class/revision)
          4'b00_11: cfg_dat_out <= #1 MISC_FUNCTIONS; // reg 0Ch (Misc Functions);
          4'b01_00: cfg_dat_out <= #1 ba0; // reg 10h (Base Address 0);
          4'b01_01: cfg_dat_out <= #1 ba1; // reg 14h (Base Address 1);
          4'b10_11: cfg_dat_out <= #1 {SUB_SYSTEM_ID,SUB_VENDOR_ID}; // reg 2Ch (SubsystemID/Subsystem VendorID);
          4'b11_11: cfg_dat_out <= #1 {16'b0,INT_PIN,int_line}; // reg 3C (Max_Lat/Min_Gnt/Interrupt Pin/ Interupt Line);
          default:  cfg_dat_out <= #1 32'b0; // unimplemented return 0's;
        endcase
      end

end



/******************************************************************/
/************    End Output Mux Section           ***************/
/******************************************************************/


   
endmodule //of config_mux
对这个程序用modelsim仿真时,想要得DEVICE_ID,VENDOR_ID时只有低16位的数,不明白是怎么一回事.看看我的激励有问题吗??我对别的仿真都得到了结果...
谢谢,

amwhlf

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