|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
【Responsibilities】
Responsibilities include performing floor planning, placement of the standard cells, memories and macros (IP), clock tree synthesis, routing, parasitic extraction, timing verification, timing closure, SI prevention and verification, DFM related such as metal/poly density fill, EM, IR drop analysis, power and ground strapping and LVS/DRC/ERC/ANT. Work with front-end and DFT engineers, backend layout designers to resolve problem and implementing ECO changes. Automate physical design flow and methodologies to achieve high efficiency and reliability. Manage the physical design projects for internal and external customer and addressing all backend issues from netlist to tape out.
【Requirements/Education】
BS/MSEE with minimum of 4+ years of hands on experience in CAD backend physical design and verification is required. Good communication skills, experience with floor planning, place & route and static timing analysis tools. Familiar with physical design strategies, methodologies and 90nm, 65nm technology issues is a plus. Be familiar with asic design flow. verilog hdl, synthesis and timing closure.
【Special Requirement】
Must have experience of hands on and complete responsibility of designing 2 chips that reached to production level. Good communication skills with good spoken/written English. Have experience with working with project of multiple teams.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks! |
|