[下载]HDVL += (HDL & HVL)

一声叹息

LBHIDDEN[0]LBHIDDENHDVL += (HDL & HVL) SystemVerilog 3.1 The Hardware Description AND Verificat
ABSTRACT
What do you get when merge the Verilog HDL (Hardware Description Language) and the VERA
HVL (Hardware Verification Language) together? You get SystemVerilog, the first full HDVL, or
Hardware Description and Verification Language!
SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard.
These enhancements provide powerful new capabilities for modeling hardware at the RTL and
system level, along with a rich set of new features for verifying model functionality. In his
keynote address at the SNUG-Boston conference in September 2002, Synopsys CEO Aart De
Geus stated that Synopsys is fully behind SystemVerilog, and will support these significant HDL
and HVL language enhancements in VCS, Design Compiler, and other applicable Synopsys tools.
This paper presents an overview of the features in the released SystemVerilog 3.0 standard, and
looks ahead at what is expected to be in the SystemVerilog 3.1 standard, which is planned for
release in June 2003. The paper also presents Synopsys’s plans to support SystemVerilog for
simulation and synthesis. The primary objectives of this paper are to show the significant
advantages of this novel HDVL approach, and to show that engineers can immediately utilize
much of the capabilities of SystemVerilog using Synopsys tools.

hoohooplay

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arens

那位朋友有System Verilog的开发工具共享一下就好了。

eetopman

感謝

power-twq

多谢

untitled

thx

ykwym

可惜没钱了

chizya

感謝