Digital ASIC design verification engineer

changlijie

Design Verification engineer                 Location: Beijing


Responsible for verification of new line of consumer application processors. Tasks include architecture and implementation of verification infrastructure for testing and regressions of module level, chips level and FPGA level designs. Tasks also include creating and implementing test plans at module and chip level



Skills/Experience Requirement:

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BSEE required, MSEE preferred

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3+ years in ASIC verification from concept through production

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Solid background in SOC design and Multi-processor based ASIC's

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Experience implementing coverage driven verification testbenches

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Fluency in C, HDL's System Verilog or Specman

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Strong shell scripting Perl/Python

Any questions pls contact changlijie-1224@hotmail.com

[ 本帖最后由 changlijie 于 2009-6-24 11:10 编辑 ]