Centec诚聘ASIC Design Engineer

清逸一枝秀

Will participate in architecting, specifying and implementing Centec Networks’s gigabit-switch ASIC and systems. Responsibilities will include micro-architecture and specifications, design, verification, and systems support.
-BSEE with 5+ years of chip design experience or MSEE with 3+ years of chip design experience
-Must be knowledgeable in ASIC methodology including HDL design, verification, synthesis, static timing verification and design.
Knowledge of switches, routers, Ethernet, TCP/IP and networking is a plus.
-Must be dynamic, growth-oriented and willing to take initiative.
-Good communication skills, team player and willing to work in a fast paced environment
为公司专用芯片研发的核心成员，参与芯片的框架设计及研发
1.有大型芯片（包括FPGA）设计、调试及流片经验
2.有丰富数字电路设计和验证的经验
3.熟练应用Verilog或VHDL等设计语言
简历请投至：jobs@centecnetworks.com