JSSC 2025 ADC 合集

icisee

A 1-GS-s 11-b Time-Interleaved SAR ADC With Robust- Fast- and Accurate Autocorrelation-Based Background Timing-Skew Calibration.pdf
A 100 - 80 Flash LiDAR Sensor With In-Pixel Zoom-Histogramming TDC and Self-Referenced Single-Slope ADC Based on Analog Counters.pdf
A 12-bit 1.5-GS-s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.pdf
A 12.8-GSs Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and 39-dB SNDR .pdf
A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined -- ADC With DAC Image Prefiltering.pdf
A 2-GS-s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk.pdf
A 2-mW 70.7-dB SNDR 200-MS-s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting.pdf
A 2.72-fJ-Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC.pdf
A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device.pdf
A 320-MHz NS TD-ADC-Assisted C-DT Hybrid Pipelined ADC With Single OTA Second-Order RAF.pdf
A 5-MS-s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden.pdf
A 5-nm 60-GS-s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz.pdf
A 6-GHz Continuous-Time Bandpass -- ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver.pdf
A 7-bit 1.75-GS-s 6.9-fJ-conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb-s SerDes Receiver.pdf
A 71.5-dB SNDR 475-MS-s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration.pdf
A 93.6-dB SNDR Fully Dynamic CT-DT Noise-Shaping SAR ADC With Closed-Loop Capacitively Coupled Two-Stage FIA.pdf
A Compact Low-Power 16 b SAR ADC Using Reservoir-Charge-Redistributed DAC and Configurable FIA-Based Comparator.pdf
A Cryo-CMOS 800-MSs 7-bit Charge-Injection SAR ADC With Only 4-fF Input Capacitance and 64-dB SFDR .pdf
A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector.pdf
A Fully Row-Column-Parallel MRAM in-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout.pdf
A Rail-to-Rail Input NS-Pipelined-SAR ADC With Self-Boosted Input Impedance and Reused Residue Amplifier for Biosignal Acquisition.pdf
A Single-Channel 12-b 2-GS-s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer.pdf
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth.pdf
An Intrinsically PVT Robust 10-bit 2.6-GS-s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme.pdf

cppvalor

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uw2233

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Billmtk

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