Engineer, Digital Verification

KT咨询-IC电子

NO.594-【猎头职位：上海需要一位   Engineer, Digital Verification】联系人：Chloe-Zhang,邮箱：hr@kthr.com，微信也可查询职位了！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

岗位职责：

1、Participate in the verification flow optimization to improve automation and productivity to produce high-quality  products.

2、Read IP/SoC design specs and integration guide to understand the verification requirements and build corresponding test plans.

3、Responses to build block/SoC testbench based on UVM methodology and create C test cases.

4、The responsibilities includes building test run and regression flow. Triage failures in regression and help designer root cause the bug.

5、Work includes Build various metrics (passing rate, functional coverage, etc) and analyze these metrics.

6、Analyze functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.

7、Take SoC RTL/GLS/LOW Power verification on fullchip for owned IPs.

岗位要求：

1、BS / MS in electrical /computer engineering and related or equivalent experience.

2、1 years working experience.

3、Programming skills in Verilog/SystemVerilog/C.

4、Has good digital verificaiton flow knowledges.

5、At least good at one of the script programing lanange : Perl, Shell,Python,makefile.

6、Strong analytical skills and learning ability.

7、Familiar with advance verification methodology (UVM, VMM, OVM, etc), tools and flow is plus.

8、Experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling is plus.

9、Familiar with low power verification and gate level verification skills is plus.

10、Excellent communication skills is plus.

福利：五险一金   年假15天   补充商业医疗