关于一个基准电压的求助

jiang_shuguo

for the kick back noise of bandgap， u may use RC to reduce (buffer is high current consumed)
for the noisy power ，u need a high psrr bandgap at about 40-50dB@ripple frequency,and  power decouple  cap is necessary。as to layout u need seperated the power line of digital and bandgap。 above solution is enough ，u do not need so many redundancy circit block cause of  not much improvement and current consumption。

jiang_shuguo

and how about your bandgap output resistance vs frequency ?

jiang_shuguo

u first figure out some concept,the giger Hz noise and low fre noise is killed out by decoulpe cap and high psrr of bandgap,only the medium fre is you care about.and the medium fre psrr of bandgap is not only depend on bandwith of bandgap.you first figure out the psrr of bandgap of all the fre.

jiang_shuguo

and the solution is better enough to resolve your issue

jiang_shuguo

is there any strict limit of area ? maybe the area is the cost.

jiang_shuguo

you also need to  check the output resistance of bandgap vs fre ,and how to figure it

jiang_shuguo

you only give the dc output resistance of bandgap ,and it is useless.

jiang_shuguo

if u have  depletion nmos available ,the ripple of power is to be unvisibility by another solution

jiang_shuguo

you need special care about the pst of medium fre .there also need a R before nmos cap ,but this R will affect you psr worst and trans result better. the output restance of bandgap is the whole of bandgap system not one branch.you leave the bandgap loop behand you head!

jiang_shuguo

So now we ture our mind ,Do  u have depletion nmos? i guess u have(process of soc chip always take depletion nmos available.)