the description“phy_and_bist_i_usb20phya CKSIE60”in path 1 relates to an original delay " 12.000f/-r " and an output delay "18.500f/-r", the sum of them is 30.500ns. but the required time is "16.000ns" which means that even path 1 is 0 delay , the slack is -14.500ns.
change your constraints and set reasonable values for the input delays and output delays and you will resolve this problem.
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发表于 2010-2-4 22:44:54
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